83 lines
2.8 KiB
C
83 lines
2.8 KiB
C
/*-
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* Copyright (c) KATO Takenori, 1997, 1998.
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*
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* All rights reserved. Unpublished rights reserved under the copyright
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* laws of Japan.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer as
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* the first lines of this file unmodified.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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static int hw_instruction_sse;
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SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
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&hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
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int cpu; /* Are we 386, 386sx, 486, etc? */
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u_int cpu_feature; /* Feature flags */
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u_int cpu_feature2; /* Feature flags */
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u_int amd_feature; /* AMD feature flags */
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u_int amd_feature2; /* AMD feature flags */
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u_int cpu_high; /* Highest arg to CPUID */
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u_int cpu_exthigh; /* Highest arg to extended CPUID */
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u_int cpu_id; /* Stepping ID */
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u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
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u_int cpu_procinfo2; /* Multicore info */
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char cpu_vendor[20]; /* CPU Origin code */
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u_int cpu_fxsr; /* SSE enabled */
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u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
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/*
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* Initialize CPU control registers
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*/
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void
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initializecpu(void)
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{
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uint64_t msr;
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if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
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load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
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cpu_fxsr = hw_instruction_sse = 1;
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}
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if ((amd_feature & AMDID_NX) != 0) {
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msr = rdmsr(MSR_EFER) | EFER_NXE;
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wrmsr(MSR_EFER, msr);
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pg_nx = PG_NX;
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}
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}
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