72143e89bb
This provides an OpenCrypto driver for Intel QuickAssist devices. The driver was initially ported from NetBSD and comes with a few improvements: - support for GMAC/AES-GCM, AES-CTR and AES-XTS, and support for SHA/HMAC-authenticated encryption - support for detaching the driver - various bug fixes - DH895X support Discussed with: jhb MFC after: 3 days Sponsored by: Rubicon Communications, LLC (Netgate) Differential Revision: https://reviews.freebsd.org/D26963
299 lines
9.9 KiB
C
299 lines
9.9 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
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/* $NetBSD: qat_c3xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
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/*
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* Copyright (c) 2019 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright(c) 2014 Intel Corporation.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#if 0
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__KERNEL_RCSID(0, "$NetBSD: qat_c3xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
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#endif
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "qatreg.h"
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#include "qat_hw17reg.h"
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#include "qat_c3xxxreg.h"
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#include "qatvar.h"
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#include "qat_hw17var.h"
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static uint32_t
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qat_c3xxx_get_accel_mask(struct qat_softc *sc)
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{
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uint32_t fusectl, strap;
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fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
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strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
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return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_C3XXX) &
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ACCEL_MASK_C3XXX);
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}
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static uint32_t
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qat_c3xxx_get_ae_mask(struct qat_softc *sc)
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{
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uint32_t fusectl, me_strap, me_disable, ssms_disabled;
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fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
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me_strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
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/* If SSMs are disabled, then disable the corresponding MEs */
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ssms_disabled = (~qat_c3xxx_get_accel_mask(sc)) & ACCEL_MASK_C3XXX;
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me_disable = 0x3;
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while (ssms_disabled) {
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if (ssms_disabled & 1)
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me_strap |= me_disable;
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ssms_disabled >>= 1;
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me_disable <<= 2;
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}
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return (~(fusectl | me_strap)) & AE_MASK_C3XXX;
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}
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static enum qat_sku
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qat_c3xxx_get_sku(struct qat_softc *sc)
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{
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switch (sc->sc_ae_num) {
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case MAX_AE_C3XXX:
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return QAT_SKU_4;
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}
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return QAT_SKU_UNKNOWN;
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}
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static uint32_t
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qat_c3xxx_get_accel_cap(struct qat_softc *sc)
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{
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uint32_t cap, legfuse, strap;
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legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
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strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
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cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
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QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
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QAT_ACCEL_CAP_CIPHER +
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QAT_ACCEL_CAP_AUTHENTICATION +
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QAT_ACCEL_CAP_COMPRESSION +
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QAT_ACCEL_CAP_ZUC +
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QAT_ACCEL_CAP_SHA3;
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if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
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cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
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cap &= ~QAT_ACCEL_CAP_CIPHER;
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}
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if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
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cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
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if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
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cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
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if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
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cap &= ~QAT_ACCEL_CAP_COMPRESSION;
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if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
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cap &= ~QAT_ACCEL_CAP_ZUC;
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if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_PKE_C3XXX)
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cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
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if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_CY_C3XXX)
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cap &= ~QAT_ACCEL_CAP_COMPRESSION;
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return cap;
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}
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static const char *
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qat_c3xxx_get_fw_uof_name(struct qat_softc *sc)
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{
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return AE_FW_UOF_NAME_C3XXX;
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}
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static void
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qat_c3xxx_enable_intr(struct qat_softc *sc)
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{
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/* Enable bundle and misc interrupts */
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qat_misc_write_4(sc, SMIAPF0_C3XXX, SMIA0_MASK_C3XXX);
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qat_misc_write_4(sc, SMIAPF1_C3XXX, SMIA1_MASK_C3XXX);
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}
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/* Worker thread to service arbiter mappings */
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static uint32_t thrd_to_arb_map[] = {
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0x12222AAA, 0x11222AAA, 0x12222AAA,
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0x11222AAA, 0x12222AAA, 0x11222AAA
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};
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static void
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qat_c3xxx_get_arb_mapping(struct qat_softc *sc, const uint32_t **arb_map_config)
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{
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int i;
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for (i = 1; i < MAX_AE_C3XXX; i++) {
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if ((~sc->sc_ae_mask) & (1 << i))
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thrd_to_arb_map[i] = 0;
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}
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*arb_map_config = thrd_to_arb_map;
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}
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static void
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qat_c3xxx_enable_error_interrupts(struct qat_softc *sc)
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{
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qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_C3XXX); /* ME0-ME3 */
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qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_C3XXX); /* ME4-ME5 */
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qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_C3XXX); /* SSM2 */
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/* Reset everything except VFtoPF1_16. */
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qat_misc_read_write_and_4(sc, ERRMSK3, VF2PF1_16_C3XXX);
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/* RI CPP bus interface error detection and reporting. */
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qat_misc_write_4(sc, RICPPINTCTL_C3XXX, RICPP_EN_C3XXX);
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/* TI CPP bus interface error detection and reporting. */
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qat_misc_write_4(sc, TICPPINTCTL_C3XXX, TICPP_EN_C3XXX);
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/* Enable CFC Error interrupts and logging. */
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qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_C3XXX, CPP_CFC_UE_C3XXX);
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}
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static void
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qat_c3xxx_disable_error_interrupts(struct qat_softc *sc)
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{
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/* ME0-ME3 */
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qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_C3XXX | ERRMSK0_CERR_C3XXX);
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/* ME4-ME5 */
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qat_misc_write_4(sc, ERRMSK1, ERRMSK1_UERR_C3XXX | ERRMSK1_CERR_C3XXX);
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/* CPP Push Pull, RI, TI, SSM0-SSM1, CFC */
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qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_C3XXX);
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/* SSM2 */
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qat_misc_write_4(sc, ERRMSK5, ERRMSK5_UERR_C3XXX);
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}
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static void
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qat_c3xxx_enable_error_correction(struct qat_softc *sc)
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{
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u_int i, mask;
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/* Enable Accel Engine error detection & correction */
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for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
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if (!(mask & 1))
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continue;
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qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_C3XXX(i),
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ENABLE_AE_ECC_ERR_C3XXX);
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qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_C3XXX(i),
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ENABLE_AE_ECC_PARITY_CORR_C3XXX);
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}
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/* Enable shared memory error detection & correction */
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for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
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if (!(mask & 1))
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continue;
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qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_C3XXX);
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qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_C3XXX);
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qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_C3XXX);
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}
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qat_c3xxx_enable_error_interrupts(sc);
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}
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const struct qat_hw qat_hw_c3xxx = {
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.qhw_sram_bar_id = BAR_SRAM_ID_C3XXX,
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.qhw_misc_bar_id = BAR_PMISC_ID_C3XXX,
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.qhw_etr_bar_id = BAR_ETR_ID_C3XXX,
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.qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C3XXX,
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.qhw_ae_offset = AE_OFFSET_C3XXX,
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.qhw_ae_local_offset = AE_LOCAL_OFFSET_C3XXX,
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.qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C3XXX,
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.qhw_num_banks = ETR_MAX_BANKS_C3XXX,
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.qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
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.qhw_num_accel = MAX_ACCEL_C3XXX,
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.qhw_num_engines = MAX_AE_C3XXX,
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.qhw_tx_rx_gap = ETR_TX_RX_GAP_C3XXX,
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.qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C3XXX,
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.qhw_clock_per_sec = CLOCK_PER_SEC_C3XXX,
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.qhw_fw_auth = true,
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.qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
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.qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
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.qhw_ring_asym_tx = 0,
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.qhw_ring_asym_rx = 8,
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.qhw_ring_sym_tx = 2,
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.qhw_ring_sym_rx = 10,
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.qhw_mof_fwname = AE_FW_MOF_NAME_C3XXX,
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.qhw_mmp_fwname = AE_FW_MMP_NAME_C3XXX,
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.qhw_prod_type = AE_FW_PROD_TYPE_C3XXX,
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.qhw_get_accel_mask = qat_c3xxx_get_accel_mask,
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.qhw_get_ae_mask = qat_c3xxx_get_ae_mask,
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.qhw_get_sku = qat_c3xxx_get_sku,
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.qhw_get_accel_cap = qat_c3xxx_get_accel_cap,
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.qhw_get_fw_uof_name = qat_c3xxx_get_fw_uof_name,
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.qhw_enable_intr = qat_c3xxx_enable_intr,
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.qhw_init_admin_comms = qat_adm_mailbox_init,
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.qhw_send_admin_init = qat_adm_mailbox_send_init,
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.qhw_init_arb = qat_arb_init,
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.qhw_get_arb_mapping = qat_c3xxx_get_arb_mapping,
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.qhw_enable_error_correction = qat_c3xxx_enable_error_correction,
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.qhw_disable_error_interrupts = qat_c3xxx_disable_error_interrupts,
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.qhw_set_ssm_wdtimer = qat_set_ssm_wdtimer,
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.qhw_check_slice_hang = qat_check_slice_hang,
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.qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
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.qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
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.qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
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};
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