kib 897bebb89d In x2APIC mode, IPI generation is atomic because it is performed by ... single ICR MSR write. This is in contrast with the xAPIC mode, where we must read current ICR value, do bit fiddling and perform two 32-bit register writes. As a consequence, there is no need to disable interrupts around ICR value calculation and write. Note that typical users of ipi_raw() and ipi_vectored() take spinlock, which already disables interrupts. For them, the change removes unneeded CLI and POPFL/Q instructions. Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks		2015-08-12 09:55:52 +00:00
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acpica	Merge ACPICA 20150619.	2015-06-18 23:14:45 +00:00
bios
cpufreq
include	Fix more style issues.	2015-08-05 17:21:42 +00:00
iommu	Typo in comment.	2015-07-20 19:51:41 +00:00
isa	Set the initial system time to a sane (as in: not end of 21st century) value when	2015-06-29 17:02:09 +00:00
pci	Reassign copyright statements on several files from Advanced	2015-04-23 14:22:20 +00:00
x86	In x2APIC mode, IPI generation is atomic because it is performed by	2015-08-12 09:55:52 +00:00
xen	Make kstack_pages a tunable on arm, x86, and powepc. On i386, the	2015-08-10 17:18:21 +00:00