8e7c909559
SoCs and various chips (including, famously, their wifi chips.) This is "just" (all 20,000 lines of it) code to enumerate the various versions of busses inside these devices, including the PCI bridge and the direct SIBA bridge found in MIPS chips. It also includes shared code for some bus operations (suspend, resume, etc); EEPROM/SROM/etc parsing and other things that are shared between chips. Eventually this'll replace the code that bwi/bwn uses for the internal bus, as well as some apparently upcoming mips74k broadcom SoC support which uses bwn! Thanks to Landon Fuller <landonf@landonf.org> for all this work! Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
224 lines
10 KiB
C
224 lines
10 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Portions of this file were derived from the bcmdevs.h header contributed by
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* Broadcom to Android's bcmdhd driver module, and the pcicfg.h header
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* distributed with Broadcom's initial brcm80211 Linux driver release.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _BHND_BHNDB_PCIREG_H_
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#define _BHND_BHNDB_PCIREG_H_
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/*
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* Common PCI/PCIE Bridge Configuration Registers.
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*
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* = MAJOR CORE REVISIONS =
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*
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* There have been four revisions to the BAR0/BAR1 memory mappings used
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* in BHND PCI/PCIE bridge cores:
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*
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* == PCI_V0 ==
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* Applies to:
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* - PCI (cid=0x804, revision <= 12)
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* BAR size: 8KB
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* Address Map:
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* [offset+ size] type description
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* [0x0000+0x1000] dynamic mapped backplane address space (window 0).
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* [0x1000+0x0800] fixed SPROM shadow
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* [0x1800+0x0800] fixed pci core registers
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*
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* == PCI_V1 ==
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* Applies to:
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* - PCI (cid=0x804, revision >= 13)
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* - PCIE (cid=0x820) with ChipCommon (revision <= 31)
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* BAR size: 16KB
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* Address Map:
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* [offset+ size] type description
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* [0x0000+0x1000] dynamic mapped backplane address space (window 0).
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* [0x1000+0x1000] fixed SPROM shadow
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* [0x2000+0x1000] fixed pci/pcie core registers
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* [0x3000+0x1000] fixed chipcommon core registers
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*
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* == PCI_V2 ==
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* Applies to:
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* - PCIE (cid=0x820) with ChipCommon (revision >= 32)
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* BAR size: 16KB
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* Address Map:
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* [offset+ size] type description
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* [0x0000+0x1000] dynamic mapped backplane address space (window 0).
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* [0x1000+0x1000] dynamic mapped backplane address space (window 1).
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* [0x2000+0x1000] fixed pci/pcie core registers
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* [0x3000+0x1000] fixed chipcommon core registers
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*
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* == PCI_V3 ==
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* Applies to:
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* - PCIE Gen 2 (cid=0x83c)
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* BAR size: 32KB?
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* Address Map:
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* [offset+ size] type description
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* [0x0000+0x1000] dynamic mapped backplane address space (window 0).
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* [0x1000+0x1000] dynamic mapped backplane address space (window 1).
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* [0x2000+0x1000] fixed pci/pcie core registers
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* [0x3000+0x1000] fixed chipcommon core registers
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* [???]
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*
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* = MINOR CORE REVISIONS =
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*
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* == PCI Cores Revision >= 3 ==
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* - Mapped GPIO CSRs into the PCI config space. Refer to
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* BHND_PCI_GPIO_*.
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*
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* == PCI/PCIE Cores Revision >= 14 ==
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* - Mapped the clock CSR into the PCI config space. Refer to
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* BHND_PCI_CLK_CTL_ST
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*
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* = Hardware Bugs =
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* == BAR1 ==
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*
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* The BHND PCI(e) cores hypothetically support an additional memory mapping
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* of the backplane address space via BAR1, but this appears to be subject
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* to a hardware bug in which BAR1 is initially configured with a 4 byte
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* length.
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*
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* A work-around for this bug may be possible by writing to the PCI core's
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* BAR1 config register (0x4e0), but this requires further research -- I've
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* found three sources for information on the BAR1 PCI core configuration that
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* may be relevant:
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* - The QLogix NetXTreme 10GB PCIe NIC seems to use the same PCIE
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* core IP block as is used in other BHND devices. The bxe(4) driver
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* contains example initialization code and register constants
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* that may apply (e.g. GRC_BAR2_CONFIG/PCI_CONFIG_2_BAR2_SIZE).
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* - The publicly available Broadcom BCM440X data sheet (440X-PG02-R)
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* appears to (partially) document a Broadcom PCI(e) core that has a
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* seemingly compatible programming model.
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* - The Android bcmdhd driver sources include a possible work-around
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* implementation (writing to 0x4e0) in dhd_pcie.c
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*/
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/* Common PCI/PCIE Config Registers */
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#define BHNDB_PCI_SPROM_CONTROL 0x88 /* sprom property control */
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#define BHNDB_PCI_BAR1_CONTROL 0x8c /* BAR1 region prefetch/burst control */
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#define BHNDB_PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
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#define BHNDB_PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
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#define BHNDB_PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
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#define BHNDB_PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
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#define BHNDB_PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
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/* PCI (non-PCIe) GPIO/Clock Config Registers */
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#define BHNDB_PCI_CLK_CTL 0xa8 /* clock control/status (pci >=rev14) */
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#define BHNDB_PCI_GPIO_IN 0xb0 /* gpio input (pci >=rev3) */
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#define BHNDB_PCI_GPIO_OUT 0xb4 /* gpio output (pci >=rev3) */
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#define BHNDB_PCI_GPIO_OUTEN 0xb8 /* gpio output enable (pci >=rev3) */
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/* Hardware revisions used to determine PCI revision */
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#define BHNDB_PCI_V0_MAX_PCI_HWREV 12
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#define BHNDB_PCI_V1_MIN_PCI_HWREV 13
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#define BHNDB_PCI_V1_MAX_CHIPC_HWREV 31
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#define BHNDB_PCI_V2_MIN_CHIPC_HWREV 32
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/**
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* Number of times to retry writing to a PCI window address register.
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*
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* On siba(4) devices, it's possible that writing a PCI window register may
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* not succeed; it's necessary to immediately read the configuration register
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* and retry if not set to the desired value.
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*/
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#define BHNDB_PCI_BARCTRL_WRITE_RETRY 50
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/* PCI_V0 */
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#define BHNDB_PCI_V0_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */
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#define BHNDB_PCI_V0_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */
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#define BHNDB_PCI_V0_BAR0_SIZE 0x2000 /* 8KB BAR0 */
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#define BHNDB_PCI_V0_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */
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#define BHNDB_PCI_V0_BAR0_WIN0_SIZE 0x1000
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#define BHNDB_PCI_V0_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
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#define BHNDB_PCI_V0_BAR0_SPROM_SIZE 0x0800
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#define BHNDB_PCI_V0_BAR0_PCIREG_OFFSET 0x1800 /* bar0 + 6K accesses pci core registers */
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#define BHNDB_PCI_V0_BAR0_PCIREG_SIZE 0x0800
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/* PCI_V1 */
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#define BHNDB_PCI_V1_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */
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#define BHNDB_PCI_V1_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */
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#define BHNDB_PCI_V1_BAR0_SIZE 0x4000 /* 16KB BAR0 */
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#define BHNDB_PCI_V1_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */
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#define BHNDB_PCI_V1_BAR0_WIN0_SIZE 0x1000
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#define BHNDB_PCI_V1_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
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#define BHNDB_PCI_V1_BAR0_SPROM_SIZE 0x1000
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#define BHNDB_PCI_V1_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */
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#define BHNDB_PCI_V1_BAR0_PCIREG_SIZE 0x1000
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#define BHNDB_PCI_V1_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */
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#define BHNDB_PCI_V1_BAR0_CCREGS_SIZE 0x1000
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/* PCI_V2 */
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#define BHNDB_PCI_V2_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */
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#define BHNDB_PCI_V2_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */
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#define BHNDB_PCI_V2_BAR0_WIN1_CONTROL 0xAC /* backplane address space accessed by BAR0/WIN1 */
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#define BHNDB_PCI_V2_BAR0_SIZE 0x4000 /* 16KB BAR0 */
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#define BHNDB_PCI_V2_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */
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#define BHNDB_PCI_V2_BAR0_WIN0_SIZE 0x1000
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#define BHNDB_PCI_V2_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */
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#define BHNDB_PCI_V2_BAR0_WIN1_SIZE 0x1000
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#define BHNDB_PCI_V2_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */
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#define BHNDB_PCI_V2_BAR0_PCIREG_SIZE 0x1000
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#define BHNDB_PCI_V2_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */
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#define BHNDB_PCI_V2_BAR0_CCREGS_SIZE 0x1000
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/* PCI_V3 */
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#define BHNDB_PCI_V3_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */
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#define BHNDB_PCI_V3_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */
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#define BHNDB_PCI_V3_BAR0_WIN1_CONTROL 0x70 /* backplane address space accessed by BAR0/WIN1 */
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#define BHNDB_PCI_V3_BAR0_SIZE 0x8000 /* 32KB BAR0 (?) */
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#define BHNDB_PCI_V3_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */
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#define BHNDB_PCI_V3_BAR0_WIN0_SIZE 0x1000
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#define BHNDB_PCI_V3_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */
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#define BHNDB_PCI_V3_BAR0_WIN1_SIZE 0x1000
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#define BHNDB_PCI_V3_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */
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#define BHNDB_PCI_V3_BAR0_PCIREG_SIZE 0x1000
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#define BHNDB_PCI_V3_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */
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#define BHNDB_PCI_V3_BAR0_CCREGS_SIZE 0x1000
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/* BHNDB_PCI_INT_STATUS */
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#define BHNDB_PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
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/* BHNDB_PCI_INT_MASK */
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#define BHNDB_PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
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#define BHNDB_PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
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#define BHNDB_PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
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/* BHNDB_PCI_SPROM_CONTROL */
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#define BHNDB_PCI_SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
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#define BHNDB_PCI_SPROM_LOCKED 0x08 /* SPROM Locked */
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#define BHNDB_PCI_SPROM_BLANK 0x04 /* indicating a blank SPROM */
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#define BHNDB_PCI_SPROM_WRITEEN 0x10 /* SPROM write enable */
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#define BHNDB_PCI_SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
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#define BHNDB_PCI_SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */
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#define BHNDB_PCI_SPROM_OTPIN_USE 0x80 /* device OTP In use */
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/* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN */
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#define BHNDB_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
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#define BHNDB_PCI_GPIO_HWRAD_OFF 0x20 /* PCI config space GPIO 13 for hw radio disable */
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#define BHNDB_PCI_GPIO_XTAL_ON 0x40 /* PCI config space GPIO 14 for Xtal power-up */
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#define BHNDB_PCI_GPIO_PLL_OFF 0x80 /* PCI config space GPIO 15 for PLL power-down */
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#endif /* _BHND_BHNDB_PCIREG_H_ */
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