e085f869d5
features of CPUs like reading/writing machine-specific registers, retrieving cpuid data, and updating microcode. - Add cpucontrol(8) utility, that provides userland access to the features of cpuctl(4). - Add subsequent manpages. The cpuctl(4) device operates as follows. The pseudo-device node cpuctlX is created for each cpu present in the systems. The pseudo-device minor number corresponds to the cpu number in the system. The cpuctl(4) pseudo- device allows a number of ioctl to be preformed, namely RDMSR/WRMSR/CPUID and UPDATE. The first pair alows the caller to read/write machine-specific registers from the correspondent CPU. cpuid data could be retrieved using the CPUID call, and microcode updates are applied via UPDATE. The permissions are inforced based on the pseudo-device file permissions. RDMSR/CPUID will be allowed when the caller has read access to the device node, while WRMSR/UPDATE will be granted only when the node is opened for writing. There're also a number of priv(9) checks. The cpucontrol(8) utility is intened to provide userland access to the cpuctl(4) device features. The utility also allows one to apply cpu microcode updates. Currently only Intel and AMD cpus are supported and were tested. Approved by: kib Reviewed by: rpaulo, cokane, Peter Jeremy MFC after: 1 month
447 lines
11 KiB
C
447 lines
11 KiB
C
/*-
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* Copyright (c) 2006-2008 Stanislav Sedov <stas@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/fcntl.h>
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#include <sys/ioccom.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/priv.h>
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#include <sys/proc.h>
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#include <sys/queue.h>
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#include <sys/sched.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/uio.h>
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#include <sys/pcpu.h>
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#include <sys/smp.h>
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#include <sys/pmckern.h>
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#include <sys/cpuctl.h>
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#include <machine/cpufunc.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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static d_open_t cpuctl_open;
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static d_ioctl_t cpuctl_ioctl;
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#define CPUCTL_VERSION 1
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#ifdef DEBUG
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# define DPRINTF(format,...) printf(format, __VA_ARGS__);
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#else
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# define DPRINTF(...)
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#endif
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#define UCODE_SIZE_MAX (10 * 1024)
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static int cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd,
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struct thread *td);
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static int cpuctl_do_cpuid(int cpu, cpuctl_cpuid_args_t *data,
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struct thread *td);
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static int cpuctl_do_update(int cpu, cpuctl_update_args_t *data,
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struct thread *td);
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static int update_intel(int cpu, cpuctl_update_args_t *args,
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struct thread *td);
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static int update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td);
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static struct cdev **cpuctl_devs;
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static MALLOC_DEFINE(M_CPUCTL, "cpuctl", "CPUCTL buffer");
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static struct cdevsw cpuctl_cdevsw = {
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.d_version = D_VERSION,
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.d_flags = D_NEEDMINOR,
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.d_open = cpuctl_open,
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.d_ioctl = cpuctl_ioctl,
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.d_name = "cpuctl",
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};
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/*
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* This function checks if specified cpu enabled or not.
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*/
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static int
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cpu_enabled(int cpu)
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{
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return (pmc_cpu_is_disabled(cpu) == 0);
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}
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/*
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* Check if the current thread is bound to a specific cpu.
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*/
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static int
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cpu_sched_is_bound(struct thread *td)
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{
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int ret;
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thread_lock(td);
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ret = sched_is_bound(td);
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thread_unlock(td);
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return (ret);
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}
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/*
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* Switch to target cpu to run.
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*/
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static void
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set_cpu(int cpu, struct thread *td)
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{
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KASSERT(cpu >= 0 && cpu < mp_ncpus && cpu_enabled(cpu),
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("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
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thread_lock(td);
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sched_bind(td, cpu);
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thread_unlock(td);
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KASSERT(td->td_oncpu == cpu,
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("[cpuctl,%d]: cannot bind to target cpu %d", __LINE__, cpu));
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}
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static void
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restore_cpu(int oldcpu, int is_bound, struct thread *td)
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{
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KASSERT(oldcpu >= 0 && oldcpu < mp_ncpus && cpu_enabled(oldcpu),
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("[cpuctl,%d]: bad cpu number %d", __LINE__, oldcpu));
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thread_lock(td);
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if (is_bound == 0)
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sched_unbind(td);
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else
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sched_bind(td, oldcpu);
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thread_unlock(td);
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}
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int
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cpuctl_ioctl(struct cdev *dev, u_long cmd, caddr_t data,
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int flags, struct thread *td)
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{
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int ret;
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int cpu = minor(dev);
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if (cpu >= mp_ncpus || !cpu_enabled(cpu)) {
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DPRINTF("[cpuctl,%d]: bad cpu number %d\n", __LINE__, cpu);
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return (ENXIO);
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}
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/* Require write flag for "write" requests. */
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if ((cmd == CPUCTL_WRMSR || cmd == CPUCTL_UPDATE) &&
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((flags & FWRITE) == 0))
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return (EPERM);
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switch (cmd) {
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case CPUCTL_RDMSR:
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ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd, td);
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break;
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case CPUCTL_WRMSR:
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ret = priv_check(td, PRIV_CPUCTL_WRMSR);
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if (ret != 0)
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goto fail;
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ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd, td);
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break;
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case CPUCTL_CPUID:
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ret = cpuctl_do_cpuid(cpu, (cpuctl_cpuid_args_t *)data, td);
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break;
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case CPUCTL_UPDATE:
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ret = priv_check(td, PRIV_CPUCTL_UPDATE);
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if (ret != 0)
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goto fail;
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ret = cpuctl_do_update(cpu, (cpuctl_update_args_t *)data, td);
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break;
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default:
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ret = EINVAL;
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break;
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}
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fail:
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return (ret);
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}
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/*
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* Actually perform cpuid operation.
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*/
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static int
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cpuctl_do_cpuid(int cpu, cpuctl_cpuid_args_t *data, struct thread *td)
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{
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int is_bound = 0;
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int oldcpu;
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KASSERT(cpu >= 0 && cpu < mp_ncpus,
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("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
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/* Explicitly clear cpuid data to avoid returning stale info. */
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bzero(data->data, sizeof(data->data));
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DPRINTF("[cpuctl,%d]: retriving cpuid level %#0x for %d cpu\n",
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__LINE__, data->level, cpu);
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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do_cpuid(data->level, data->data);
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restore_cpu(oldcpu, is_bound, td);
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return (0);
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}
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/*
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* Actually perform MSR operations.
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*/
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static int
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cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd, struct thread *td)
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{
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int is_bound = 0;
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int oldcpu;
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int ret;
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KASSERT(cpu >= 0 && cpu < mp_ncpus,
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("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
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/*
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* Explicitly clear cpuid data to avoid returning stale
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* info
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*/
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data->data = 0;
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DPRINTF("[cpuctl,%d]: operating on MSR %#0x for %d cpu\n", __LINE__,
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data->msr, cpu);
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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ret = cmd == CPUCTL_RDMSR ? rdmsr_safe(data->msr, &data->data) :
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wrmsr_safe(data->msr, data->data);
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restore_cpu(oldcpu, is_bound, td);
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return (ret);
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}
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/*
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* Actually perform microcode update.
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*/
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static int
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cpuctl_do_update(int cpu, cpuctl_update_args_t *data, struct thread *td)
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{
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cpuctl_cpuid_args_t args = {
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.level = 0,
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};
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char vendor[13];
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int ret;
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KASSERT(cpu >= 0 && cpu < mp_ncpus,
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("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
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DPRINTF("[cpuctl,%d]: XXX %d", __LINE__, cpu);
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ret = cpuctl_do_cpuid(cpu, &args, td);
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if (ret != 0) {
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DPRINTF("[cpuctl,%d]: cannot retrive cpuid info for cpu %d",
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__LINE__, cpu);
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return (ENXIO);
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}
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((uint32_t *)vendor)[0] = args.data[1];
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((uint32_t *)vendor)[1] = args.data[3];
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((uint32_t *)vendor)[2] = args.data[2];
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vendor[12] = '\0';
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if (strncmp(vendor, INTEL_VENDOR_ID, sizeof(INTEL_VENDOR_ID)) == 0)
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ret = update_intel(cpu, data, td);
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else if(strncmp(vendor, INTEL_VENDOR_ID, sizeof(AMD_VENDOR_ID)) == 0)
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ret = update_amd(cpu, data, td);
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else
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ret = ENXIO;
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return (ret);
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}
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static int
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update_intel(int cpu, cpuctl_update_args_t *args, struct thread *td)
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{
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void *ptr = NULL;
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uint64_t rev0, rev1;
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uint32_t tmp[4];
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int is_bound = 0;
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int oldcpu;
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int ret;
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if (args->size == 0 || args->data == NULL) {
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DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__);
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return (EINVAL);
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}
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if (args->size > UCODE_SIZE_MAX) {
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DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__);
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return (EINVAL);
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}
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/*
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* 16 byte alignment required.
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*/
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ptr = malloc(args->size + 16, M_CPUCTL, M_WAITOK);
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ptr = (void *)(16 + ((intptr_t)ptr & ~0xf));
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if (copyin(args->data, ptr, args->size) != 0) {
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DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed",
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__LINE__, args->data, ptr, args->size);
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ret = EFAULT;
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goto fail;
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}
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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critical_enter();
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rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current micorcode revision. */
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/*
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* Perform update.
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*/
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wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr));
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wrmsr_safe(MSR_BIOS_SIGN, 0);
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/*
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* Serialize instruction flow.
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*/
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do_cpuid(0, tmp);
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critical_exit();
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rdmsr_safe(MSR_BIOS_SIGN, &rev1); /* Get new micorcode revision. */
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restore_cpu(oldcpu, is_bound, td);
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if (rev1 > rev0)
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ret = 0;
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else
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ret = EEXIST;
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fail:
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if (ptr != NULL)
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contigfree(ptr, args->size, M_CPUCTL);
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return (ret);
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}
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static int
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update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td)
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{
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void *ptr = NULL;
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uint32_t tmp[4];
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int is_bound = 0;
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int oldcpu;
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int ret;
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if (args->size == 0 || args->data == NULL) {
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DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__);
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return (EINVAL);
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}
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if (args->size > UCODE_SIZE_MAX) {
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DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__);
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return (EINVAL);
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}
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/*
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* XXX Might not require contignous address space - needs check
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*/
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ptr = contigmalloc(args->size, M_CPUCTL, 0, 0, 0xffffffff, 16, 0);
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if (ptr == NULL) {
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DPRINTF("[cpuctl,%d]: cannot allocate %zd bytes of memory",
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__LINE__, args->size);
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return (ENOMEM);
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}
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if (copyin(args->data, ptr, args->size) != 0) {
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DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed",
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__LINE__, args->data, ptr, args->size);
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ret = EFAULT;
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goto fail;
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}
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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critical_enter();
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/*
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* Perform update.
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*/
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wrmsr_safe(MSR_K8_UCODE_UPDATE, (uintptr_t)args->data);
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/*
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* Serialize instruction flow.
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*/
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do_cpuid(0, tmp);
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critical_exit();
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restore_cpu(oldcpu, is_bound, td);
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ret = 0;
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fail:
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if (ptr != NULL)
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contigfree(ptr, args->size, M_CPUCTL);
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return (ret);
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}
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int
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cpuctl_open(struct cdev *dev, int flags, int fmt __unused, struct thread *td)
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{
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int ret = 0;
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int cpu;
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cpu = minor(dev);
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if (cpu >= mp_ncpus || !cpu_enabled(cpu)) {
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DPRINTF("[cpuctl,%d]: incorrect cpu number %d\n", __LINE__,
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cpu);
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return (ENXIO);
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}
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if (flags & FWRITE)
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ret = securelevel_gt(td->td_ucred, 0);
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return (ret);
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}
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static int
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cpuctl_modevent(module_t mod __unused, int type, void *data __unused)
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{
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int cpu;
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switch(type) {
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case MOD_LOAD:
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if ((cpu_feature & CPUID_MSR) == 0) {
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if (bootverbose)
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printf("cpuctl: not available.\n");
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return (ENODEV);
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}
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if (bootverbose)
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printf("cpuctl: access to MSR registers/cpuid info.\n");
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cpuctl_devs = (struct cdev **)malloc(sizeof(void *) * mp_ncpus,
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M_CPUCTL, M_WAITOK | M_ZERO);
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if (cpuctl_devs == NULL) {
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DPRINTF("[cpuctl,%d]: cannot allocate memory\n",
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__LINE__);
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return (ENOMEM);
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}
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for (cpu = 0; cpu < mp_ncpus; cpu++)
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if (cpu_enabled(cpu))
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cpuctl_devs[cpu] = make_dev(&cpuctl_cdevsw, cpu,
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UID_ROOT, GID_KMEM, 0640, "cpuctl%d", cpu);
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break;
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case MOD_UNLOAD:
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for (cpu = 0; cpu < mp_ncpus; cpu++) {
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if (cpuctl_devs[cpu] != NULL)
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destroy_dev(cpuctl_devs[cpu]);
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}
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free(cpuctl_devs, M_CPUCTL);
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break;
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case MOD_SHUTDOWN:
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break;
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default:
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return (EOPNOTSUPP);
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}
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return (0);
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}
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DEV_MODULE(cpuctl, cpuctl_modevent, NULL);
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MODULE_VERSION(cpuctl, CPUCTL_VERSION);
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