41b420910c
#define COMPAT_PCI_DRIVER(name,data) DATA_SET(pcidevice_set,data) .. to 2.2.x and 3.x if people think it's worth it. Driver writers can do this if it's not defined. (The reason for this is that I'm trying to progressively eliminate use of linker_sets where it hurts modularity and runtime load capability, and these DATA_SET's keep getting in the way.)
188 lines
5.2 KiB
C
188 lines
5.2 KiB
C
/*
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* Copyright (c) 1997 by Simon Shapiro
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* dptpci.c: PCI Bus Attachment for DPT SCSI HBAs
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*/
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#ident "$Id: dpt_pci.c,v 1.12 1999/04/24 20:13:58 peter Exp $"
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#include "opt_devfs.h"
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#include "opt_dpt.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <sys/kernel.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <machine/bus_memio.h>
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#include <machine/bus_pio.h>
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#include <machine/bus.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/dpt/dpt.h>
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#include <pci/dpt_pci.h>
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#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */
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#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */
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#define ISA_PRIMARY_WD_ADDRESS 0x1f8
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/* Global variables */
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/* Function Prototypes */
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static const char *dpt_pci_probe(pcici_t tag, pcidi_t type);
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static void dpt_pci_attach(pcici_t config_id, int unit);
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extern struct cdevsw dpt_cdevsw;
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static struct pci_device dpt_pci_driver =
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{
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"dpt",
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dpt_pci_probe,
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dpt_pci_attach,
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&dpt_unit,
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NULL
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};
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COMPAT_PCI_DRIVER(dpt_pci, dpt_pci_driver);
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/*
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* Probe the PCI device.
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* Some of this work will have to be duplicated in _attach
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* because we do not know for sure how the two relate.
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*/
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static const char *
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dpt_pci_probe(pcici_t tag, pcidi_t type)
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{
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u_int32_t class;
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#ifndef PCI_COMMAND_MASTER_ENABLE
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#define PCI_COMMAND_MASTER_ENABLE 0x00000004
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#endif
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#ifndef PCI_SUBCLASS_MASS_STORAGE_SCSI
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#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000
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#endif
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class = pci_conf_read(tag, PCI_CLASS_REG);
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if (((type & 0xffff0000) >> 16) == DPT_DEVICE_ID
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&& (class & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE
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&& (class & PCI_SUBCLASS_MASK) == PCI_SUBCLASS_MASS_STORAGE_SCSI)
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return ("DPT Caching SCSI RAID Controller");
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return (NULL);
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}
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static void
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dpt_pci_attach(pcici_t config_id, int unit)
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{
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dpt_softc_t *dpt;
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vm_offset_t vaddr;
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#ifdef DPT_ALLOW_MEMIO
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vm_offset_t paddr;
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#endif
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u_int16_t io_base;
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bus_space_tag_t tag;
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bus_space_handle_t bsh;
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u_int32_t command;
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int s;
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vaddr = NULL;
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command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
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#ifdef DPT_ALLOW_MEMIO
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if ((command & PCI_COMMAND_MEM_ENABLE) == 0
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|| (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0)
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#endif
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if ((command & PCI_COMMAND_IO_ENABLE) == 0
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|| (pci_map_port(config_id, PCI_BASEADR0, &io_base)) == 0)
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return;
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/*
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* If the DPT is mapped as an IDE controller,
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* let it be IDE controller
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*/
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if (io_base == ISA_PRIMARY_WD_ADDRESS - 0x10) {
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#ifdef DPT_DEBUG_WARN
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printf("dpt%d: Mapped as an IDE controller. "
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"Disabling SCSI setup\n", unit);
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#endif
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return;
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}
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/* XXX Should be passed in by parent bus */
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/* XXX Why isn't the 0x10 offset incorporated into the reg defs? */
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if (vaddr != 0) {
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tag = I386_BUS_SPACE_MEM;
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bsh = vaddr + 0x10;
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} else {
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tag = I386_BUS_SPACE_IO;
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bsh = io_base + 0x10;
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}
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if ((dpt = dpt_alloc(unit, tag, bsh)) == NULL)
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return; /* XXX PCI code should take return status */
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/* Allocate a dmatag representing the capabilities of this attachment */
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/* XXX Should be a child of the PCI bus dma tag */
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if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/0, /*boundary*/0,
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/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
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/*highaddr*/BUS_SPACE_MAXADDR,
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/*filter*/NULL, /*filterarg*/NULL,
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/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
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/*nsegments*/BUS_SPACE_UNRESTRICTED,
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/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
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/*flags*/0, &dpt->parent_dmat) != 0) {
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dpt_free(dpt);
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return;
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}
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if (pci_map_int(config_id, dpt_intr, (void *)dpt, &cam_imask) == 0) {
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dpt_free(dpt);
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return;
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}
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s = splcam();
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if (dpt_init(dpt) != 0) {
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dpt_free(dpt);
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return;
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}
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/* Register with the XPT */
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dpt_attach(dpt);
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splx(s);
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}
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