48ee531892
Allwinner H5 is an H3 (arm32) with Cortex A53 cores. Add support for it and enable it in GENERIC kernel config Tested on: OrangePi PC2
305 lines
7.4 KiB
C
305 lines
7.4 KiB
C
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner oscillator clock
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include "clkdev_if.h"
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#define CCU_BASE 0x01c20000
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#define CCU_SIZE 0x400
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#define PRCM_BASE 0x01f01400
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#define PRCM_SIZE 0x200
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#define SYSCTRL_BASE 0x01c00000
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#define SYSCTRL_SIZE 0x34
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struct aw_ccu_softc {
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struct simplebus_softc sc;
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bus_space_tag_t bst;
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bus_space_handle_t ccu_bsh;
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bus_space_handle_t prcm_bsh;
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bus_space_handle_t sysctrl_bsh;
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struct mtx mtx;
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int flags;
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};
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#define CLOCK_CCU (1 << 0)
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#define CLOCK_PRCM (1 << 1)
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#define CLOCK_SYSCTRL (1 << 2)
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10", CLOCK_CCU },
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{ "allwinner,sun5i-a13", CLOCK_CCU },
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{ "allwinner,sun7i-a20", CLOCK_CCU },
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{ "allwinner,sun6i-a31", CLOCK_CCU },
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{ "allwinner,sun6i-a31s", CLOCK_CCU },
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{ "allwinner,sun50i-a64", CLOCK_CCU },
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{ "allwinner,sun50i-h5", CLOCK_CCU },
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{ "allwinner,sun8i-a33", CLOCK_CCU },
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{ "allwinner,sun8i-a83t", CLOCK_CCU|CLOCK_PRCM|CLOCK_SYSCTRL },
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{ "allwinner,sun8i-h2-plus", CLOCK_CCU|CLOCK_PRCM },
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{ "allwinner,sun8i-h3", CLOCK_CCU|CLOCK_PRCM },
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{ NULL, 0 }
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};
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static int
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aw_ccu_check_addr(struct aw_ccu_softc *sc, bus_addr_t addr,
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bus_space_handle_t *pbsh, bus_size_t *poff)
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{
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if (addr >= CCU_BASE && addr < (CCU_BASE + CCU_SIZE) &&
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(sc->flags & CLOCK_CCU) != 0) {
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*poff = addr - CCU_BASE;
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*pbsh = sc->ccu_bsh;
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return (0);
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}
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if (addr >= PRCM_BASE && addr < (PRCM_BASE + PRCM_SIZE) &&
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(sc->flags & CLOCK_PRCM) != 0) {
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*poff = addr - PRCM_BASE;
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*pbsh = sc->prcm_bsh;
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return (0);
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}
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if (addr >= SYSCTRL_BASE && addr < (SYSCTRL_BASE + SYSCTRL_SIZE) &&
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(sc->flags & CLOCK_SYSCTRL) != 0) {
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*poff = addr - SYSCTRL_BASE;
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*pbsh = sc->sysctrl_bsh;
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return (0);
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}
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return (EINVAL);
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}
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static int
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aw_ccu_write_4(device_t dev, bus_addr_t addr, uint32_t val)
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{
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struct aw_ccu_softc *sc;
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bus_space_handle_t bsh;
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bus_size_t reg;
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sc = device_get_softc(dev);
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if (aw_ccu_check_addr(sc, addr, &bsh, ®) != 0)
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return (EINVAL);
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mtx_assert(&sc->mtx, MA_OWNED);
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bus_space_write_4(sc->bst, bsh, reg, val);
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return (0);
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}
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static int
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aw_ccu_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
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{
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struct aw_ccu_softc *sc;
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bus_space_handle_t bsh;
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bus_size_t reg;
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sc = device_get_softc(dev);
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if (aw_ccu_check_addr(sc, addr, &bsh, ®) != 0)
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return (EINVAL);
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mtx_assert(&sc->mtx, MA_OWNED);
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*val = bus_space_read_4(sc->bst, bsh, reg);
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return (0);
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}
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static int
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aw_ccu_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
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{
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struct aw_ccu_softc *sc;
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bus_space_handle_t bsh;
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bus_size_t reg;
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uint32_t val;
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sc = device_get_softc(dev);
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if (aw_ccu_check_addr(sc, addr, &bsh, ®) != 0)
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return (EINVAL);
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mtx_assert(&sc->mtx, MA_OWNED);
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val = bus_space_read_4(sc->bst, bsh, reg);
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val &= ~clr;
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val |= set;
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bus_space_write_4(sc->bst, bsh, reg, val);
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return (0);
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}
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static void
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aw_ccu_device_lock(device_t dev)
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{
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struct aw_ccu_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mtx);
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}
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static void
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aw_ccu_device_unlock(device_t dev)
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{
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struct aw_ccu_softc *sc;
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sc = device_get_softc(dev);
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mtx_unlock(&sc->mtx);
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}
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static const struct ofw_compat_data *
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aw_ccu_search_compatible(void)
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{
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const struct ofw_compat_data *compat;
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phandle_t root;
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root = OF_finddevice("/");
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for (compat = compat_data; compat->ocd_str != NULL; compat++)
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if (ofw_bus_node_is_compatible(root, compat->ocd_str))
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break;
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return (compat);
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}
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static int
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aw_ccu_probe(device_t dev)
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{
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const char *name;
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name = ofw_bus_get_name(dev);
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if (name == NULL || strcmp(name, "clocks") != 0)
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return (ENXIO);
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if (aw_ccu_search_compatible()->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner Clock Control Unit");
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return (BUS_PROBE_SPECIFIC);
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}
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static int
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aw_ccu_attach(device_t dev)
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{
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struct aw_ccu_softc *sc;
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phandle_t node, child;
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device_t cdev;
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int error;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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simplebus_init(dev, node);
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sc->flags = aw_ccu_search_compatible()->ocd_data;
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/*
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* Map registers. The DT doesn't have a "reg" property
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* for the /clocks node and child nodes have conflicting "reg"
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* properties.
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*/
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sc->bst = bus_get_bus_tag(dev);
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if (sc->flags & CLOCK_CCU) {
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error = bus_space_map(sc->bst, CCU_BASE, CCU_SIZE, 0,
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&sc->ccu_bsh);
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if (error != 0) {
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device_printf(dev, "couldn't map CCU: %d\n", error);
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return (error);
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}
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}
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if (sc->flags & CLOCK_PRCM) {
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error = bus_space_map(sc->bst, PRCM_BASE, PRCM_SIZE, 0,
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&sc->prcm_bsh);
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if (error != 0) {
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device_printf(dev, "couldn't map PRCM: %d\n", error);
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return (error);
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}
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}
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if (sc->flags & CLOCK_SYSCTRL) {
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error = bus_space_map(sc->bst, SYSCTRL_BASE, SYSCTRL_SIZE, 0,
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&sc->sysctrl_bsh);
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if (error != 0) {
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device_printf(dev, "couldn't map SYSCTRL: %d\n", error);
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return (error);
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}
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}
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mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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/* Attach child devices */
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for (child = OF_child(node); child > 0; child = OF_peer(child)) {
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cdev = simplebus_add_device(dev, child, 0, NULL, -1, NULL);
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if (cdev != NULL)
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device_probe_and_attach(cdev);
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}
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return (bus_generic_attach(dev));
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}
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static device_method_t aw_ccu_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aw_ccu_probe),
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DEVMETHOD(device_attach, aw_ccu_attach),
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/* clkdev interface */
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DEVMETHOD(clkdev_write_4, aw_ccu_write_4),
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DEVMETHOD(clkdev_read_4, aw_ccu_read_4),
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DEVMETHOD(clkdev_modify_4, aw_ccu_modify_4),
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DEVMETHOD(clkdev_device_lock, aw_ccu_device_lock),
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DEVMETHOD(clkdev_device_unlock, aw_ccu_device_unlock),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(aw_ccu, aw_ccu_driver, aw_ccu_methods,
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sizeof(struct aw_ccu_softc), simplebus_driver);
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static devclass_t aw_ccu_devclass;
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EARLY_DRIVER_MODULE(aw_ccu, simplebus, aw_ccu_driver, aw_ccu_devclass,
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0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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MODULE_VERSION(aw_ccu, 1);
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