8b24253e00
the NAND flash controller. Add the AR934x NAND flash controller reset routines. (It's different on subsequent SoCs.) Tested: * AR9344, Atheros DB120 reference platform Obtained from: OpenWRT
170 lines
5.3 KiB
C
170 lines
5.3 KiB
C
/*-
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* Copyright (c) 2010 Adrian Chadd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef __AR71XX_CPUDEF_H__
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#define __AR71XX_CPUDEF_H__
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struct ar71xx_cpu_def {
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void (* detect_mem_size) (void);
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void (* detect_sys_frequency) (void);
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void (* ar71xx_chip_device_stop) (uint32_t);
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void (* ar71xx_chip_device_start) (uint32_t);
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int (* ar71xx_chip_device_stopped) (uint32_t);
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void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t);
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void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t);
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void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode);
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void (* ar71xx_chip_ddr_flush_ge) (int);
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uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int);
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/*
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* From Linux - Handling this IRQ is a bit special.
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* AR71xx - AR71XX_DDR_REG_FLUSH_PCI
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* AR724x - AR724X_DDR_REG_FLUSH_PCIE
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* AR91xx - AR91XX_DDR_REG_FLUSH_WMAC
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*
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* These are set when STATUSF_IP2 is set in regiser c0.
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* This flush is done before the IRQ is handled to make
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* sure the driver correctly sees any memory updates.
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*/
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void (* ar71xx_chip_ddr_flush_ip2) (void);
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/*
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* The USB peripheral init code is subtly different for
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* each chip.
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*/
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void (* ar71xx_chip_init_usb_peripheral) (void);
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void (* ar71xx_chip_reset_ethernet_switch) (void);
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void (* ar71xx_chip_reset_wmac) (void);
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void (* ar71xx_chip_init_gmac) (void);
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void (* ar71xx_chip_reset_nfc) (int);
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};
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extern struct ar71xx_cpu_def * ar71xx_cpu_ops;
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static inline void ar71xx_detect_sys_frequency(void)
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{
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ar71xx_cpu_ops->detect_sys_frequency();
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}
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static inline void ar71xx_device_stop(uint32_t mask)
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{
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ar71xx_cpu_ops->ar71xx_chip_device_stop(mask);
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}
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static inline void ar71xx_device_start(uint32_t mask)
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{
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ar71xx_cpu_ops->ar71xx_chip_device_start(mask);
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}
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static inline int ar71xx_device_stopped(uint32_t mask)
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{
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return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask);
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}
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static inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll)
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{
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ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll);
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}
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static inline void ar71xx_device_set_mii_speed(int unit, int speed)
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{
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ar71xx_cpu_ops->ar71xx_chip_set_mii_speed(unit, speed);
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}
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static inline void ar71xx_device_set_mii_if(int unit, ar71xx_mii_mode mii_cfg)
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{
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ar71xx_cpu_ops->ar71xx_chip_set_mii_if(unit, mii_cfg);
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}
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static inline void ar71xx_device_flush_ddr_ge(int unit)
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{
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ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit);
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}
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static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed)
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{
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return (ar71xx_cpu_ops->ar71xx_chip_get_eth_pll(unit, speed));
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}
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static inline void ar71xx_init_usb_peripheral(void)
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{
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ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
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}
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static inline void ar71xx_reset_ethernet_switch(void)
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{
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if (ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch)
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ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch();
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}
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static inline void ar71xx_reset_wmac(void)
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{
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if (ar71xx_cpu_ops->ar71xx_chip_reset_wmac)
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ar71xx_cpu_ops->ar71xx_chip_reset_wmac();
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}
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static inline void ar71xx_init_gmac(void)
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{
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if (ar71xx_cpu_ops->ar71xx_chip_init_gmac)
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ar71xx_cpu_ops->ar71xx_chip_init_gmac();
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}
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static inline void ar71xx_device_ddr_flush_ip2(void)
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{
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ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2();
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}
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static inline void ar71xx_reset_nfc(int active)
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{
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if (ar71xx_cpu_ops->ar71xx_chip_reset_nfc)
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ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active);
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}
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/* XXX shouldn't be here! */
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extern uint32_t u_ar71xx_refclk;
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extern uint32_t u_ar71xx_cpu_freq;
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extern uint32_t u_ar71xx_ahb_freq;
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extern uint32_t u_ar71xx_ddr_freq;
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extern uint32_t u_ar71xx_uart_freq;
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extern uint32_t u_ar71xx_wdt_freq;
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extern uint32_t u_ar71xx_mdio_freq;
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static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
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static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
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static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
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static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }
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static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; }
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static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; }
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static inline uint64_t ar71xx_mdio_freq(void) { return u_ar71xx_mdio_freq; }
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#endif
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