Colin Percival 8b4553119e Adjust dangerous-shared-cache-detection logic from "all shared data ... caches are dangerous" to "a shared L1 data cache is dangerous". This is a compromise between paranoia and performance: Unlike the L1 cache, nobody has publicly demonstrated a cryptographic side channel which exploits the L2 cache -- this is harder due to the larger size, lower bandwidth, and greater associativity -- and prohibiting shared L2 caches turns Intel Core Duo processors into Intel Core Solo processors. As before, the 'machdep.hyperthreading_allowed' sysctl will allow even the L1 data cache to be shared. Discussed with: jhb, scottl Security: See FreeBSD-SA-05:09.htt for background material.		2006-04-24 21:17:01 +00:00
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acpica	If the XSDT address in the RSDP for an ACPI 2.0 machine is NULL, then fall	2006-03-27 15:59:48 +00:00
amd64	Adjust dangerous-shared-cache-detection logic from "all shared data	2006-04-24 21:17:01 +00:00
compile
conf	Move AHC_REG_PRETTY_PRINT and AHD_REG_PRETTY_PRINT below	2006-04-24 08:44:34 +00:00
ia32	Simplify system time accounting for profiling.	2006-02-08 08:09:17 +00:00
include	Introduce minidumps. Full physical memory crash dumps are still available	2006-04-21 04:24:50 +00:00
isa	Rework how we wire up interrupt sources to CPUs:	2006-02-28 22:24:55 +00:00
linux32	regen: fix of linuxolator with testing in a cross-build	2006-03-20 18:54:29 +00:00
pci	MFi386: rename pcib_devclass to hostb_devclass (cosmetic here)	2006-03-13 23:58:40 +00:00
Makefile