8baedda6af
Only PCI and on-board ISA peripherials are supported at this time. This support has been only lightly tested due to a lack of response to my call for testers on the freebsd-alpha mailing list. It works quite well on the one AS2100 on which it has been tested, but it may not work on an AS2100A and should therefore be regarded as experimental.
173 lines
7.6 KiB
C
173 lines
7.6 KiB
C
/*
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* Copyright (c) 2000 Doug Rabson & Andrew Gallatin
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Registers in the T2 CBUS-to-PCI bridge as used in the SABLE
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* systems.
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*/
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#define REGVAL(r) (*(volatile int32_t *) \
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ALPHA_PHYS_TO_K0SEG(r + t2_csr_base))
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#define REGVAL64(r) (*(volatile int64_t *) \
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ALPHA_PHYS_TO_K0SEG(r + t2_csr_base))
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#define SABLE_BASE 0x0UL /* offset of SABLE CSRs */
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#define LYNX_BASE 0x8000000000UL /* offset of LYNX CSRs */
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#define CBUS_BASE 0x380000000 /* CBUS CSRs */
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#define T2_PCI_SIO 0x3a0000000 /* PCI sparse I/O space */
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#define T2_PCI_CONF 0x390000000 /* PCI configuration space */
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#define T2_PCI_SPARSE 0x200000000 /* PCI sparse memory space */
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#define T2_PCI_DENSE 0x3c0000000 /* PCI dense memory space */
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#define T2_IOCSR (CBUS_BASE + 0xe000000)
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/* Low word */
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#define T2_IOCSRL_EL 0x00000002UL /* loopback enable */
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#define T2_IOCSRL_ESMV 0x00000004UL /* enable state machine visibility */
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#define T2_IOCSRL_PDBP 0x00000008UL /* PCI drive bad parity */
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#define T2_IOCSRL_SLOT0 0x00000030UL /* PCI slot 0 present bits */
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#define T2_IOCSRL_PINT 0x00000040UL /* PCI interrupt */
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#define T2_IOCSRL_ENTLBEC 0x00000080UL /* enable TLB error check */
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#define T2_IOCSRL_ENCCDMA 0x00000100UL /* enable CXACK for DMA */
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#define T2_IOCSRL_ENXXCHG 0x00000400UL /* enable exclusive exchange for EV5 */
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#define T2_IOCSRL_CAWWP0 0x00001000UL /* CBUS command/address write wrong parity 0 */
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#define T2_IOCSRL_CAWWP2 0x00002000UL /* CBUS command/address write wrong parity 2 */
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#define T2_IOCSRL_CDWWPE 0x00004000UL /* CBUS data write wrong parity even */
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#define T2_IOCSRL_SLOT2 0x00008000UL /* PCI slot 2 present bit */
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#define T2_IOCSRL_PSERR 0x00010000UL /* power supply error */
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#define T2_IOCSRL_MBA7 0x00020000UL /* MBA7 asserted */
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#define T2_IOCSRL_SLOT1 0x000c0000UL /* PCI slot 1 present bits */
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#define T2_IOCSRL_PDWWP1 0x00100000UL /* PCI DMA write wrong parity HW1 */
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#define T2_IOCSRL_PDWWP0 0x00200000UL /* PCI DMA write wrong parity HW0 */
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#define T2_IOCSRL_PBR 0x00400000UL /* PCI bus reset */
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#define T2_IOCSRL_PIR 0x00800000UL /* PCI interface reset */
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#define T2_IOCSRL_ENCOI 0x01000000UL /* enable NOACK, CUCERR and out-of-sync int */
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#define T2_IOCSRL_EPMS 0x02000000UL /* enable PCI memory space */
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#define T2_IOCSRL_ETLB 0x04000000UL /* enable TLB */
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#define T2_IOCSRL_EACC 0x08000000UL /* enable atomic CBUS cycles */
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#define T2_IOCSRL_ITLB 0x10000000UL /* flush TLB */
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#define T2_IOCSRL_ECPC 0x20000000UL /* enable CBUS parity check */
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#define T2_IOCSRL_CIR 0x40000000UL /* CBUS interface reset */
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#define T2_IOCSRL_EPL 0x80000000UL /* enable PCI lock */
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/* High word */
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#define T2_IOCSRH_CBBCE 0x00000001UL /* CBUS back-to-back cycle enable */
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#define T2_IOCSRH_TM 0x0000000eUL /* T2 revision number */
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#define T2_IOCSRH_SMVL 0x00000070UL /* state machine visibility select */
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#define T2_IOCSRH_SLOT2 0x00000080UL /* PCI slot 2 present bit */
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#define T2_IOCSRH_EPR 0x00000100UL /* enable passive release */
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#define T2_IOCSRH_CAWWP1 0x00001000UL /* cbus command/address write wrong parity 1 */
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#define T2_IOCSRH_CAWWP3 0x00002000UL /* cbus command/address write wrong parity 3 */
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#define T2_IOCSRH_DWWPO 0x00004000UL /* CBUS data write wrong parity odd */
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#define T2_IOCSRH_PRM 0x00100000UL /* PCI read multiple */
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#define T2_IOCSRH_PWM 0x00200000UL /* PCI write multiple */
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#define T2_IOCSRH_FPRDPED 0x00400000UL /* force PCI RDPE detect */
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#define T2_IOCSRH_PFAPED 0x00800000UL /* force PCI APE detect */
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#define T2_IOCSRH_FPWDPED 0x01000000UL /* force PCI WDPE detect */
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#define T2_IOCSRH_EPNMI 0x02000000UL /* enable PCI NMI */
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#define T2_IOCSRH_EPDTI 0x04000000UL /* enable PCI DTI */
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#define T2_IOCSRH_EPSEI 0x08000000UL /* enable PCI SERR interrupt */
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#define T2_IOCSRH_EPPEI 0x10000000UL /* enable PCI PERR interrupt */
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#define T2_IOCSRH_ERDPC 0x20000000UL /* enable PCI RDP interrupt */
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#define T2_IOCSRH_EADPC 0x40000000UL /* enable PCI AP interrupt */
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#define T2_IOCSRH_EWDPC 0x80000000UL /* enable PCI WDP interrupt */
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#define T2_CERR1 (CBUS_BASE + 0xe000020)
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#define T2_CERR2 (CBUS_BASE + 0xe000040)
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#define T2_CERR3 (CBUS_BASE + 0xe000060)
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#define T2_PERR1 (CBUS_BASE + 0xe000080)
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#define T2_PERR1_PWDPE 0x00000001 /* PCI write data parity error */
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#define T2_PERR1_PAPE 0x00000002 /* PCI address parity error */
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#define T2_PERR1_PRDPE 0x00000004 /* PCI read data parity error */
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#define T2_PERR1_PPE 0x00000008 /* PCI parity error */
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#define T2_PERR1_PSE 0x00000010 /* PCI system error */
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#define T2_PERR1_PDTE 0x00000020 /* PCI device timeout error */
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#define T2_PERR1_NMI 0x00000040 /* PCI NMI */
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#define T2_PERR2 (CBUS_BASE + 0xe0000a0)
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#define T2_PSCR (CBUS_BASE + 0xe0000c0)
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#define T2_HAE0_1 (CBUS_BASE + 0xe0000e0)
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#define T2_HAE0_2 (CBUS_BASE + 0xe000100)
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#define T2_HBASE (CBUS_BASE + 0xe000120)
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#define T2_WBASE1 (CBUS_BASE + 0xe000140)
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#define T2_WMASK1 (CBUS_BASE + 0xe000160)
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#define T2_TBASE1 (CBUS_BASE + 0xe000180)
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#define T2_WBASE2 (CBUS_BASE + 0xe0001a0)
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#define T2_WMASK2 (CBUS_BASE + 0xe0001c0)
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#define T2_TBASE2 (CBUS_BASE + 0xe0001e0)
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#define T2_TLBBR (CBUS_BASE + 0xe000200)
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#define T2_HAE0_3 (CBUS_BASE + 0xe000240)
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#define T2_HAE0_4 (CBUS_BASE + 0xe000280)
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/*
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* DMA window constants, section 5.2.1.1.1 of the
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* Sable I/O Specification
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*/
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#define T2_WINDOW_ENABLE 0x00080000
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#define T2_WINDOW_DISABLE 0x00000000
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#define T2_WINDOW_SG 0x00040000
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#define T2_WINDOW_DIRECT 0x00000000
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#define T2_WMASK_2G 0x7ff00000
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#define T2_WMASK_1G 0x3ff00000
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#define T2_WMASK_512M 0x1ff00000
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#define T2_WMASK_256M 0x0ff00000
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#define T2_WMASK_128M 0x07f00000
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#define T2_WMASK_64M 0x03f00000
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#define T2_WMASK_32M 0x01f00000
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#define T2_WMASK_16M 0x00f00000
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#define T2_WMASK_8M 0x00700000
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#define T2_WMASK_4M 0x00300000
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#define T2_WMASK_2M 0x00100000
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#define T2_WMASK_1M 0x00000000
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#define T2_WSIZE_2G 0x80000000
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#define T2_WSIZE_1G 0x40000000
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#define T2_WSIZE_512M 0x20000000
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#define T2_WSIZE_256M 0x10000000
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#define T2_WSIZE_128M 0x08000000
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#define T2_WSIZE_64M 0x04000000
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#define T2_WSIZE_32M 0x02000000
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#define T2_WSIZE_16M 0x01000000
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#define T2_WSIZE_8M 0x00800000
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#define T2_WSIZE_4M 0x00400000
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#define T2_WSIZE_2M 0x00200000
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#define T2_WSIZE_1M 0x00100000
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#define T2_WSIZE_0M 0x00000000
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#define T2_TBASE_SHIFT 1
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#define MASTER_ICU 0x535
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#define SLAVE0_ICU 0x537
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#define SLAVE1_ICU 0x53b
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#define SLAVE2_ICU 0x53d
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#define SLAVE3_ICU 0x53f
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