95f13176f5
When the system has more than a single PCI domain, the bus numbers are not unique, thus they cannot be used for "pci" device numbering. Change bus numbers to -1 (i.e. to-be-determined automatically) wherever the code did not care about domains. Reviewed by: jhb Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3406
775 lines
19 KiB
C
775 lines
19 KiB
C
/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
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/*-
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI configuration support for gt I/O Processor chip.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/interrupt.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/pmap.h>
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#include <mips/malta/maltareg.h>
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#include <mips/malta/gtreg.h>
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#include <mips/malta/gtvar.h>
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#include <isa/isareg.h>
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#include <dev/ic/i8259.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <mips/malta/gt_pci_bus_space.h>
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#define ICU_LEN 16 /* number of ISA IRQs */
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/*
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* XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file
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* from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions.
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*/
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#define PIC_OCW1 1
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#define PIC_OCW2 0
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#define PIC_OCW3 0
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#define OCW2_SELECT 0
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#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
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#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
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#define OCW3_POLL_PENDING (1U << 7)
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/*
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* Galileo controller's registers are LE so convert to then
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* to/from native byte order. We rely on boot loader or emulator
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* to set "swap bytes" configuration correctly for us
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*/
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#define GT_PCI_DATA(v) htole32((v))
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#define GT_HOST_DATA(v) le32toh((v))
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struct gt_pci_softc;
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struct gt_pci_intr_cookie {
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int irq;
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struct gt_pci_softc *sc;
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};
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struct gt_pci_softc {
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device_t sc_dev;
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_ioh_icu1;
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bus_space_handle_t sc_ioh_icu2;
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bus_space_handle_t sc_ioh_elcr;
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int sc_busno;
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struct rman sc_mem_rman;
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struct rman sc_io_rman;
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struct rman sc_irq_rman;
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unsigned long sc_mem;
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bus_space_handle_t sc_io;
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struct resource *sc_irq;
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struct intr_event *sc_eventstab[ICU_LEN];
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struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN];
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uint16_t sc_imask;
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uint16_t sc_elcr;
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uint16_t sc_reserved;
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void *sc_ih;
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};
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static void gt_pci_set_icus(struct gt_pci_softc *);
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static int gt_pci_intr(void *v);
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static int gt_pci_probe(device_t);
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static int gt_pci_attach(device_t);
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static int gt_pci_activate_resource(device_t, device_t, int, int,
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struct resource *);
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static int gt_pci_setup_intr(device_t, device_t, struct resource *,
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int, driver_filter_t *, driver_intr_t *, void *, void **);
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static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
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static int gt_pci_maxslots(device_t );
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static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int,
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uint32_t *);
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static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
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static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
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static struct resource * gt_pci_alloc_resource(device_t, device_t, int,
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int *, u_long, u_long, u_long, u_int);
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static void
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gt_pci_mask_irq(void *source)
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{
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struct gt_pci_intr_cookie *cookie = source;
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struct gt_pci_softc *sc = cookie->sc;
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int irq = cookie->irq;
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sc->sc_imask |= (1 << irq);
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sc->sc_elcr |= (1 << irq);
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gt_pci_set_icus(sc);
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}
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static void
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gt_pci_unmask_irq(void *source)
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{
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struct gt_pci_intr_cookie *cookie = source;
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struct gt_pci_softc *sc = cookie->sc;
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int irq = cookie->irq;
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/* Enable it, set trigger mode. */
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sc->sc_imask &= ~(1 << irq);
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sc->sc_elcr &= ~(1 << irq);
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gt_pci_set_icus(sc);
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}
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static void
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gt_pci_set_icus(struct gt_pci_softc *sc)
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{
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/* Enable the cascade IRQ (2) if 8-15 is enabled. */
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if ((sc->sc_imask & 0xff00) != 0xff00)
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sc->sc_imask &= ~(1U << 2);
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else
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sc->sc_imask |= (1U << 2);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
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sc->sc_imask & 0xff);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
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(sc->sc_imask >> 8) & 0xff);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
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sc->sc_elcr & 0xff);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
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(sc->sc_elcr >> 8) & 0xff);
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}
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static int
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gt_pci_intr(void *v)
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{
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struct gt_pci_softc *sc = v;
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struct intr_event *event;
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int irq;
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for (;;) {
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
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OCW3_SEL | OCW3_P);
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irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
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if ((irq & OCW3_POLL_PENDING) == 0)
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{
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return FILTER_HANDLED;
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}
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irq = OCW3_POLL_IRQ(irq);
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if (irq == 2) {
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
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PIC_OCW3, OCW3_SEL | OCW3_P);
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irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
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PIC_OCW3);
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if (irq & OCW3_POLL_PENDING)
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irq = OCW3_POLL_IRQ(irq) + 8;
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else
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irq = 2;
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}
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event = sc->sc_eventstab[irq];
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if (!event || TAILQ_EMPTY(&event->ie_handlers))
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continue;
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/* TODO: frame instead of NULL? */
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intr_event_handle(event, NULL);
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/* XXX: Log stray IRQs */
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/* Send a specific EOI to the 8259. */
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if (irq > 7) {
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
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PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
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OCW2_ILS(irq & 7));
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irq = 2;
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}
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
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OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
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}
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return FILTER_HANDLED;
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}
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static int
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gt_pci_probe(device_t dev)
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{
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device_set_desc(dev, "GT64120 PCI bridge");
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return (0);
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}
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static int
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gt_pci_attach(device_t dev)
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{
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uint32_t busno;
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struct gt_pci_softc *sc = device_get_softc(dev);
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int rid;
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busno = 0;
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sc->sc_dev = dev;
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sc->sc_busno = busno;
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sc->sc_st = mips_bus_space_generic;
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/* Use KSEG1 to access IO ports for it is uncached */
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sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
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sc->sc_io_rman.rm_type = RMAN_ARRAY;
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sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
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/*
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* First 256 bytes are ISA's registers: e.g. i8259's
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* So do not use them for general purpose PCI I/O window
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*/
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if (rman_init(&sc->sc_io_rman) != 0 ||
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rman_manage_region(&sc->sc_io_rman, 0x100, 0xffff) != 0) {
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panic("gt_pci_attach: failed to set up I/O rman");
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}
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/* Use KSEG1 to access PCI memory for it is uncached */
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sc->sc_mem = MIPS_PHYS_TO_KSEG1(MALTA_PCIMEM1_BASE);
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory";
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if (rman_init(&sc->sc_mem_rman) != 0 ||
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rman_manage_region(&sc->sc_mem_rman,
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sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) {
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panic("gt_pci_attach: failed to set up memory rman");
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}
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sc->sc_irq_rman.rm_type = RMAN_ARRAY;
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sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs";
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
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panic("gt_pci_attach: failed to set up IRQ rman");
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/*
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* Map the PIC/ELCR registers.
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*/
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#if 0
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if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
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device_printf(dev, "unable to map ELCR registers\n");
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if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
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device_printf(dev, "unable to map ICU1 registers\n");
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if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
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device_printf(dev, "unable to map ICU2 registers\n");
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#else
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sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
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sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1;
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sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2;
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#endif
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/* All interrupts default to "masked off". */
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sc->sc_imask = 0xffff;
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/* All interrupts default to edge-triggered. */
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sc->sc_elcr = 0;
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/*
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* Initialize the 8259s.
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*/
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/* reset, program device, 4 bytes */
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
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ICW1_RESET | ICW1_IC4);
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/*
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* XXX: values from NetBSD's <dev/ic/i8259reg.h>
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*/
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
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0/*XXX*/);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
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1 << 2);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
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ICW4_8086);
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/* mask all interrupts */
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
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sc->sc_imask & 0xff);
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/* enable special mask mode */
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
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OCW3_SEL | OCW3_ESMM | OCW3_SMM);
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/* read IRR by default */
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
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OCW3_SEL | OCW3_RR);
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/* reset, program device, 4 bytes */
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
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ICW1_RESET | ICW1_IC4);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
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0/*XXX*/);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
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1 << 2);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
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ICW4_8086);
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/* mask all interrupts */
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
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sc->sc_imask & 0xff);
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/* enable special mask mode */
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
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OCW3_SEL | OCW3_ESMM | OCW3_SMM);
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/* read IRR by default */
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bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
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OCW3_SEL | OCW3_RR);
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/*
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* Default all interrupts to edge-triggered.
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*/
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bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
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sc->sc_elcr & 0xff);
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bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
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(sc->sc_elcr >> 8) & 0xff);
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/*
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* Some ISA interrupts are reserved for devices that
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* we know are hard-wired to certain IRQs.
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*/
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sc->sc_reserved =
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(1U << 0) | /* timer */
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(1U << 1) | /* keyboard controller (keyboard) */
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(1U << 2) | /* PIC cascade */
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(1U << 3) | /* COM 2 */
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(1U << 4) | /* COM 1 */
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(1U << 6) | /* floppy */
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(1U << 7) | /* centronics */
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(1U << 8) | /* RTC */
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(1U << 9) | /* I2C */
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(1U << 12) | /* keyboard controller (mouse) */
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(1U << 14) | /* IDE primary */
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(1U << 15); /* IDE secondary */
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/* Hook up our interrupt handler. */
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if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
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MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1,
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RF_SHAREABLE | RF_ACTIVE)) == NULL) {
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device_printf(dev, "unable to allocate IRQ resource\n");
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return ENXIO;
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}
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if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
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gt_pci_intr, NULL, sc, &sc->sc_ih))) {
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device_printf(dev,
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"WARNING: unable to register interrupt handler\n");
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return ENXIO;
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}
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/* Initialize memory and i/o rmans. */
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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gt_pci_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static int
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gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func,
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int reg, uint32_t *addr)
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{
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*addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
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return (0);
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}
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static uint32_t
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gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int bytes)
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{
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struct gt_pci_softc *sc = device_get_softc(dev);
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uint32_t data;
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uint32_t addr;
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uint32_t shift, mask;
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if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
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return (uint32_t)(-1);
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|
/* Clear cause register bits. */
|
|
GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
|
|
GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
|
|
/*
|
|
* Galileo system controller is special
|
|
*/
|
|
if ((bus == 0) && (slot == 0))
|
|
data = GT_PCI_DATA(GT_REGVAL(GT_PCI0_CFG_DATA));
|
|
else
|
|
data = GT_REGVAL(GT_PCI0_CFG_DATA);
|
|
|
|
/* Check for master abort. */
|
|
if (GT_HOST_DATA(GT_REGVAL(GT_INTR_CAUSE)) & (GTIC_MASABORT0 | GTIC_TARABORT0))
|
|
data = (uint32_t) -1;
|
|
|
|
switch(reg % 4)
|
|
{
|
|
case 3:
|
|
shift = 24;
|
|
break;
|
|
case 2:
|
|
shift = 16;
|
|
break;
|
|
case 1:
|
|
shift = 8;
|
|
break;
|
|
default:
|
|
shift = 0;
|
|
break;
|
|
}
|
|
|
|
switch(bytes)
|
|
{
|
|
case 1:
|
|
mask = 0xff;
|
|
data = (data >> shift) & mask;
|
|
break;
|
|
case 2:
|
|
mask = 0xffff;
|
|
if(reg % 4 == 0)
|
|
data = data & mask;
|
|
else
|
|
data = (data >> 16) & mask;
|
|
break;
|
|
case 4:
|
|
break;
|
|
default:
|
|
panic("gt_pci_readconfig: wrong bytes count");
|
|
break;
|
|
}
|
|
#if 0
|
|
printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
|
|
bus, slot, func, reg, data, bytes);
|
|
#endif
|
|
|
|
return (data);
|
|
}
|
|
|
|
static void
|
|
gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
|
uint32_t data, int bytes)
|
|
{
|
|
struct gt_pci_softc *sc = device_get_softc(dev);
|
|
uint32_t addr;
|
|
uint32_t reg_data;
|
|
uint32_t shift, mask;
|
|
|
|
if(bytes != 4)
|
|
{
|
|
reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4);
|
|
|
|
shift = 8 * (reg & 3);
|
|
|
|
switch(bytes)
|
|
{
|
|
case 1:
|
|
mask = 0xff;
|
|
data = (reg_data & ~ (mask << shift)) | (data << shift);
|
|
break;
|
|
case 2:
|
|
mask = 0xffff;
|
|
if(reg % 4 == 0)
|
|
data = (reg_data & ~mask) | data;
|
|
else
|
|
data = (reg_data & ~ (mask << shift)) |
|
|
(data << shift);
|
|
break;
|
|
case 4:
|
|
break;
|
|
default:
|
|
panic("gt_pci_readconfig: wrong bytes count");
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
|
|
return;
|
|
|
|
/* The galileo has problems accessing device 31. */
|
|
if (bus == 0 && slot == 31)
|
|
return;
|
|
|
|
/* XXX: no support for bus > 0 yet */
|
|
if (bus > 0)
|
|
return;
|
|
|
|
/* Clear cause register bits. */
|
|
GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
|
|
|
|
GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
|
|
|
|
/*
|
|
* Galileo system controller is special
|
|
*/
|
|
if ((bus == 0) && (slot == 0))
|
|
GT_REGVAL(GT_PCI0_CFG_DATA) = GT_PCI_DATA(data);
|
|
else
|
|
GT_REGVAL(GT_PCI0_CFG_DATA) = data;
|
|
|
|
#if 0
|
|
printf("PCICONF_WRITE(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
|
|
bus, slot, func, reg, data, bytes);
|
|
#endif
|
|
|
|
}
|
|
|
|
static int
|
|
gt_pci_route_interrupt(device_t pcib, device_t dev, int pin)
|
|
{
|
|
int bus;
|
|
int device;
|
|
int func;
|
|
/* struct gt_pci_softc *sc = device_get_softc(pcib); */
|
|
bus = pci_get_bus(dev);
|
|
device = pci_get_slot(dev);
|
|
func = pci_get_function(dev);
|
|
/*
|
|
* XXXMIPS: We need routing logic. This is just a stub .
|
|
*/
|
|
switch (device) {
|
|
case 9: /*
|
|
* PIIX4 IDE adapter. HW IRQ0
|
|
*/
|
|
return 0;
|
|
case 11: /* Ethernet */
|
|
return 10;
|
|
default:
|
|
device_printf(pcib, "no IRQ mapping for %d/%d/%d/%d\n", bus, device, func, pin);
|
|
|
|
}
|
|
return (0);
|
|
|
|
}
|
|
|
|
static int
|
|
gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
|
{
|
|
struct gt_pci_softc *sc = device_get_softc(dev);
|
|
switch (which) {
|
|
case PCIB_IVAR_DOMAIN:
|
|
*result = 0;
|
|
return (0);
|
|
case PCIB_IVAR_BUS:
|
|
*result = sc->sc_busno;
|
|
return (0);
|
|
|
|
}
|
|
return (ENOENT);
|
|
}
|
|
|
|
static int
|
|
gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
|
|
{
|
|
struct gt_pci_softc * sc = device_get_softc(dev);
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
sc->sc_busno = result;
|
|
return (0);
|
|
}
|
|
return (ENOENT);
|
|
}
|
|
|
|
static struct resource *
|
|
gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
|
|
u_long start, u_long end, u_long count, u_int flags)
|
|
{
|
|
struct gt_pci_softc *sc = device_get_softc(bus);
|
|
struct resource *rv = NULL;
|
|
struct rman *rm;
|
|
bus_space_handle_t bh = 0;
|
|
|
|
switch (type) {
|
|
case SYS_RES_IRQ:
|
|
rm = &sc->sc_irq_rman;
|
|
break;
|
|
case SYS_RES_MEMORY:
|
|
rm = &sc->sc_mem_rman;
|
|
bh = sc->sc_mem;
|
|
break;
|
|
case SYS_RES_IOPORT:
|
|
rm = &sc->sc_io_rman;
|
|
bh = sc->sc_io;
|
|
break;
|
|
default:
|
|
return (NULL);
|
|
}
|
|
|
|
rv = rman_reserve_resource(rm, start, end, count, flags, child);
|
|
if (rv == NULL)
|
|
return (NULL);
|
|
rman_set_rid(rv, *rid);
|
|
if (type != SYS_RES_IRQ) {
|
|
bh += (rman_get_start(rv));
|
|
|
|
rman_set_bustag(rv, gt_pci_bus_space);
|
|
rman_set_bushandle(rv, bh);
|
|
if (flags & RF_ACTIVE) {
|
|
if (bus_activate_resource(child, type, *rid, rv)) {
|
|
rman_release_resource(rv);
|
|
return (NULL);
|
|
}
|
|
}
|
|
}
|
|
return (rv);
|
|
}
|
|
|
|
static int
|
|
gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
bus_space_handle_t p;
|
|
int error;
|
|
|
|
if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
|
|
error = bus_space_map(rman_get_bustag(r),
|
|
rman_get_bushandle(r), rman_get_size(r), 0, &p);
|
|
if (error)
|
|
return (error);
|
|
rman_set_bushandle(r, p);
|
|
}
|
|
return (rman_activate_resource(r));
|
|
}
|
|
|
|
static int
|
|
gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
|
|
int flags, driver_filter_t *filt, driver_intr_t *handler,
|
|
void *arg, void **cookiep)
|
|
{
|
|
struct gt_pci_softc *sc = device_get_softc(dev);
|
|
struct intr_event *event;
|
|
int irq, error;
|
|
|
|
irq = rman_get_start(ires);
|
|
if (irq >= ICU_LEN || irq == 2)
|
|
panic("%s: bad irq or type", __func__);
|
|
|
|
event = sc->sc_eventstab[irq];
|
|
sc->sc_intr_cookies[irq].irq = irq;
|
|
sc->sc_intr_cookies[irq].sc = sc;
|
|
if (event == NULL) {
|
|
error = intr_event_create(&event,
|
|
(void *)&sc->sc_intr_cookies[irq], 0, irq,
|
|
gt_pci_mask_irq, gt_pci_unmask_irq,
|
|
NULL, NULL, "gt_pci intr%d:", irq);
|
|
if (error)
|
|
return 0;
|
|
sc->sc_eventstab[irq] = event;
|
|
}
|
|
|
|
intr_event_add_handler(event, device_get_nameunit(child), filt,
|
|
handler, arg, intr_priority(flags), flags, cookiep);
|
|
|
|
gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
|
|
void *cookie)
|
|
{
|
|
struct gt_pci_softc *sc = device_get_softc(dev);
|
|
int irq;
|
|
|
|
irq = rman_get_start(res);
|
|
gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
|
|
|
|
return (intr_event_remove_handler(cookie));
|
|
}
|
|
|
|
static device_method_t gt_pci_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, gt_pci_probe),
|
|
DEVMETHOD(device_attach, gt_pci_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, gt_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, gt_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, gt_pci_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, gt_pci_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, gt_pci_maxslots),
|
|
DEVMETHOD(pcib_read_config, gt_pci_read_config),
|
|
DEVMETHOD(pcib_write_config, gt_pci_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t gt_pci_driver = {
|
|
"pcib",
|
|
gt_pci_methods,
|
|
sizeof(struct gt_pci_softc),
|
|
};
|
|
|
|
static devclass_t gt_pci_devclass;
|
|
|
|
DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);
|