0757a4afb5
The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
107 lines
2.9 KiB
ArmAsm
107 lines
2.9 KiB
ArmAsm
/*-
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "assym.s"
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#include <machine/param.h>
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#include <machine/asm.h>
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#include <machine/spr.h>
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#include <machine/psl.h>
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#include <machine/pte.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <machine/tlb.h>
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.text
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/*
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* void remap_ccsrbar(vm_offset_t old_ccsrbar_va, vm_offset_t new_ccsrbar_va,
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* vm_offset_t new_ccsrbar_pa)
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*
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* r3 - old_ccsrbar_va
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* r4 - new_ccsrbar_va
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* r5 - new_ccsrbar_pa
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*/
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ENTRY(remap_ccsrbar)
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/*
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* CCSRBAR updating sequence according
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* to section 4.3.1.1.1 of MPC8555E RM.
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*/
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/* Read current value of CCSRBAR */
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lwz %r6, 0(%r3)
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isync
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/* Write new value */
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rlwinm %r6, %r5, 20, 12, 23
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stw %r6, 0(%r3)
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/*
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* Read from address that is outside of CCSRBAR space.
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* We have RAM locations available at KERNBASE.
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*/
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lis %r7, KERNBASE@ha
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addi %r7, %r7, KERNBASE@l
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lwz %r6, 0(%r7)
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isync
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/* Read value of CCSRBAR from new location */
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lwz %r6, 0(%r4)
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isync
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blr
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/*
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* void switch_to_as0(void)
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*/
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ENTRY(switch_to_as0)
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mflr %r5 /* Save LR */
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mfmsr %r3
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lis %r6, (PSL_IS | PSL_DS)@ha
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ori %r6, %r6, (PSL_IS | PSL_DS)@l
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not %r6, %r6
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and %r3, %r3, %r6 /* Clear IS/DS bits */
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bl 1f
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1: mflr %r4 /* Use current address */
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addi %r4, %r4, 20 /* Increment to instruction after rfi */
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi
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mtlr %r5 /* Restore LR */
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blr
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/*
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* void load_pid0(tlbtid_t)
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*/
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ENTRY(load_pid0)
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mtspr SPR_PID0, %r3
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isync
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blr
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