8cbc8d3dd1
When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe or Crypto controllers and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note, that other outer-cache operations are not removed, as they may be needed for certain situations, such as booting secondary CPUs. Moreover, in order to enable IO coherent operation, the decision whether to use L2 cache maintenance callbacks is done in busdma layer, which was enabled in one of the previous commits. Submitted by: Michal Mazur <mkm@semihalf.com> Marcin Wojtas <mw@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Differential revision: https://reviews.freebsd.org/D11245
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