7fd348080f
transmitter, but not both at the same time. This patch: - Adds a dev.pcm.0.internal_codec sysctl node for selecting between internal and external codec - Changes playback sample rate from 96 kHz to 48 kHz for HDMI compatibility - Enables i2s clock on codec access Reviewed by: br Differential Revision: https://reviews.freebsd.org/D8960
103 lines
5.3 KiB
C
103 lines
5.3 KiB
C
/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define CODEC_RGADW 0x00 /* Address, data in and write command */
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#define RGADW_ICRST (1 << 31) /* Reset internal CODEC */
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#define RGADW_RGWR (1 << 16) /* Issue a write command to CODEC */
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#define RGADW_RGADDR_S 8 /* CODEC register's address. */
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#define RGADW_RGADDR_M (0x7f << RGADW_RGADDR_S)
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#define RGADW_RGDIN_S 0 /* CODEC register data to write */
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#define RGADW_RGDIN_M (0xff << RGADW_RGDIN_S)
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#define CODEC_RGDATA 0x04 /* The data read out */
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#define SR 0x00 /* Status Register */
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#define SR2 0x01 /* Status Register 2 */
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#define MR 0x07 /* Mode status register */
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#define AICR_DAC 0x08 /* DAC Audio Interface Control Register */
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#define DAC_ADWL_S 6 /* Audio Data Word Length for DAC path. */
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#define DAC_ADWL_M (0x3 << DAC_ADWL_S)
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#define DAC_ADWL_16 (0 << DAC_ADWL_S)
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#define AICR_DAC_SB (1 << 4) /* DAC audio interface in power-down mode */
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#define AUDIOIF_S 0
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#define AUDIOIF_M (0x3 << AUDIOIF_S)
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#define AUDIOIF_I2S 0x3 /* I2S interface */
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#define AUDIOIF_DSP 0x2 /* DSP interface */
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#define AUDIOIF_LJ 0x1 /* Left-justified interface */
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#define AUDIOIF_P 0x0 /* Parallel interface */
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#define AICR_ADC 0x09 /* ADC Audio Interface Control Register */
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#define CR_LO 0x0B /* Differential line-out Control Register */
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#define CR_HP 0x0D /* HeadPhone Control Register */
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#define HP_MUTE (1 << 7) /* no signal on headphone outputs */
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#define HP_SB (1 << 4) /* power-down */
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#define CR_DMIC 0x10 /* Digital Microphone register */
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#define CR_MIC1 0x11 /* Microphone1 Control register */
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#define CR_MIC2 0x12 /* Microphone2 Control register */
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#define CR_LI1 0x13 /* Control Register for line1 inputs */
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#define CR_LI2 0x14 /* Control Register for line2 inputs */
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#define CR_DAC 0x17 /* DAC Control Register */
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#define DAC_MUTE (1 << 7) /* puts the DAC in soft mute mode */
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#define DAC_SB (1 << 4) /* power-down */
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#define CR_ADC 0x18 /* ADC Control Register */
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#define CR_MIX 0x19 /* Digital Mixer Control Register */
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#define DR_MIX 0x1A /* Digital Mixer Data Register */
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#define CR_VIC 0x1B /* Control Register for the ViC */
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#define VIC_SB_SLEEP (1 << 1) /* sleep mode */
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#define VIC_SB (1 << 0) /* complete power-down */
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#define CR_CK 0x1C /* Clock Control Register */
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#define FCR_DAC 0x1D /* DAC Frequency Control Register */
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#define FCR_DAC_48 8 /* 48 kHz. */
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#define FCR_DAC_96 10 /* 96 kHz. */
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#define FCR_ADC 0x20 /* ADC Frequency Control Register */
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#define CR_TIMER_MSB 0x21 /* MSB of programmable counter */
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#define CR_TIMER_LSB 0x22 /* LSB of programmable counter */
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#define ICR 0x23 /* Interrupt Control Register */
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#define IMR 0x24 /* Interrupt Mask Register */
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#define IFR 0x25 /* Interrupt Flag Register */
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#define IMR2 0x26 /* Interrupt Mask Register 2 */
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#define IFR2 0x27 /* Interrupt Flag Register 2 */
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#define GCR_HPL 0x28 /* Left channel headphone Control Gain Register */
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#define GCR_HPR 0x29 /* Right channel headphone Control Gain Register */
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#define GCR_LIBYL 0x2A /* Left channel bypass line Control Gain Register */
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#define GCR_LIBYR 0x2B /* Right channel bypass line Control Gain Register */
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#define GCR_DACL 0x2C /* Left channel DAC Gain Control Register */
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#define GCR_DACR 0x2D /* Right channel DAC Gain Control Register */
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#define GCR_MIC1 0x2E /* Microphone 1 Gain Control Register */
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#define GCR_MIC2 0x2F /* Microphone 2 Gain Control Register */
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#define GCR_ADCL 0x30 /* Left ADC Gain Control Register */
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#define GCR_ADCR 0x31 /* Right ADC Gain Control Register */
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#define GCR_MIXDACL 0x34 /* DAC Digital Mixer Control Register */
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#define GCR_MIXDACR 0x35 /* DAC Digital Mixer Control Register */
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#define GCR_MIXADCL 0x36 /* ADC Digital Mixer Control Register */
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#define GCR_MIXADCR 0x37 /* ADC Digital Mixer Control Register */
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#define CR_ADC_AGC 0x3A /* Automatic Gain Control Register */
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#define DR_ADC_AGC 0x3B /* Automatic Gain Control Data Register */
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