227 lines
7.5 KiB
C
227 lines
7.5 KiB
C
/*-
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* Copyright (c) 2000 Michael Smith
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Register names, bit definitions, structure names and members are
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* identical with those in the Linux driver where possible and sane
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* for simplicity's sake. (The TW_ prefix has become TWE_)
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* Some defines that are clearly irrelevant to FreeBSD have been
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* removed.
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*/
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/* control register bit definitions */
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#define TWE_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
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#define TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
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#define TWE_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
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#define TWE_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
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#define TWE_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
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#define TWE_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
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#define TWE_CONTROL_CLEAR_ERROR_STATUS 0x00000200
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#define TWE_CONTROL_ISSUE_SOFT_RESET 0x00000100
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#define TWE_CONTROL_ENABLE_INTERRUPTS 0x00000080
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#define TWE_CONTROL_DISABLE_INTERRUPTS 0x00000040
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#define TWE_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
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#define TWE_SOFT_RESET(sc) TWE_CONTROL(sc, TWE_CONTROL_ISSUE_SOFT_RESET | \
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TWE_CONTROL_CLEAR_HOST_INTERRUPT | \
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TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
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TWE_CONTROL_MASK_COMMAND_INTERRUPT | \
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TWE_CONTROL_MASK_RESPONSE_INTERRUPT | \
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TWE_CONTROL_CLEAR_ERROR_STATUS | \
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TWE_CONTROL_DISABLE_INTERRUPTS)
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/* status register bit definitions */
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#define TWE_STATUS_MAJOR_VERSION_MASK 0xF0000000
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#define TWE_STATUS_MINOR_VERSION_MASK 0x0F000000
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#define TWE_STATUS_PCI_PARITY_ERROR 0x00800000
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#define TWE_STATUS_QUEUE_ERROR 0x00400000
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#define TWE_STATUS_MICROCONTROLLER_ERROR 0x00200000
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#define TWE_STATUS_PCI_ABORT 0x00100000
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#define TWE_STATUS_HOST_INTERRUPT 0x00080000
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#define TWE_STATUS_ATTENTION_INTERRUPT 0x00040000
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#define TWE_STATUS_COMMAND_INTERRUPT 0x00020000
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#define TWE_STATUS_RESPONSE_INTERRUPT 0x00010000
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#define TWE_STATUS_COMMAND_QUEUE_FULL 0x00008000
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#define TWE_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
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#define TWE_STATUS_MICROCONTROLLER_READY 0x00002000
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#define TWE_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
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#define TWE_STATUS_ALL_INTERRUPTS 0x000F0000
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#define TWE_STATUS_CLEARABLE_BITS 0x00D00000
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#define TWE_STATUS_EXPECTED_BITS 0x00002000
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#define TWE_STATUS_UNEXPECTED_BITS 0x00F80000
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/* for use with the %b printf format */
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#define TWE_STATUS_BITS_DESCRIPTION \
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"\20\15CQEMPTY\16UCREADY\17RQEMPTY\20CQFULL\21RINTR\22CINTR\23AINTR\24HINTR\25PCIABRT\26MCERR\27QERR\30PCIPERR\n"
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/* detect inconsistencies in the status register */
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#define TWE_STATUS_ERRORS(x) \
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(((x & TWE_STATUS_PCI_ABORT) || \
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(x & TWE_STATUS_PCI_PARITY_ERROR) || \
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(x & TWE_STATUS_QUEUE_ERROR) || \
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(x & TWE_STATUS_MICROCONTROLLER_ERROR)) && \
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(x & TWE_STATUS_MICROCONTROLLER_READY))
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/* Response queue bit definitions */
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#define TWE_RESPONSE_ID_MASK 0x00000FF0
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/* PCI related defines */
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#define TWE_IO_CONFIG_REG 0x10
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#define TWE_DEVICE_NAME "3ware Storage Controller"
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#define TWE_VENDOR_ID 0x13C1
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#define TWE_DEVICE_ID 0x1000
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/* command packet opcodes */
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#define TWE_OP_NOP 0x0
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#define TWE_OP_INIT_CONNECTION 0x1
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#define TWE_OP_READ 0x2
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#define TWE_OP_WRITE 0x3
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#define TWE_OP_VERIFY 0x4
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#define TWE_OP_GET_PARAM 0x12
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#define TWE_OP_SET_PARAM 0x13
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#define TWE_OP_SECTOR_INFO 0x1a
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#define TWE_OP_AEN_LISTEN 0x1c
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/* asynchronous event notification (AEN) codes */
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#define TWE_AEN_QUEUE_EMPTY 0x0000
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#define TWE_AEN_SOFT_RESET 0x0001
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#define TWE_AEN_DEGRADED_MIRROR 0x0002
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#define TWE_AEN_CONTROLLER_ERROR 0x0003
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#define TWE_AEN_REBUILD_FAIL 0x0004
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#define TWE_AEN_REBUILD_DONE 0x0005
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#define TWE_AEN_QUEUE_FULL 0x00ff
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#define TWE_AEN_TABLE_UNDEFINED 0x15
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/* misc defines */
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#define TWE_ALIGNMENT 0x200
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#define TWE_MAX_UNITS 16
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#define TWE_COMMAND_ALIGNMENT_MASK 0x1ff
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#define TWE_INIT_MESSAGE_CREDITS 0x100
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#define TWE_INIT_COMMAND_PACKET_SIZE 0x3
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#define TWE_MAX_SGL_LENGTH 62
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#define TWE_Q_LENGTH 256
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#define TWE_Q_START 0
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#define TWE_MAX_RESET_TRIES 3
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#define TWE_UNIT_INFORMATION_TABLE_BASE 0x300
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#define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */
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#define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */
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#define TWE_IOCTL 0x80
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#define TWE_MAX_AEN_TRIES 100
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/* wrappers for bus-space actions */
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#define TWE_CONTROL(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x0, (u_int32_t)val)
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#define TWE_STATUS(sc) (u_int32_t)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0x4)
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#define TWE_COMMAND_QUEUE(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x8, (u_int32_t)val)
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#define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0xc)
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/* scatter/gather list entry */
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typedef struct
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{
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u_int32_t address;
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u_int32_t length;
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} TWE_SG_Entry __attribute__ ((packed));
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/* command packet - must be TWE_ALIGNMENT aligned */
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typedef struct
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{
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u_int8_t opcode:5;
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u_int8_t sgl_offset:3;
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u_int8_t size;
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u_int8_t request_id;
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u_int8_t unit:4;
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u_int8_t host_id:4;
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u_int8_t status;
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u_int8_t flags;
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u_int16_t count; /* block count, parameter count, message credits */
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union {
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struct {
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u_int32_t lba;
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TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
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} io __attribute__ ((packed));
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struct {
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TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
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} param;
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struct {
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u_int32_t response_queue_pointer;
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} init_connection;
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} args;
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} TWE_Command __attribute__ ((packed));
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/* argument to TWE_OP_GET/SET_PARAM */
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typedef struct
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{
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u_int16_t table_id;
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u_int8_t parameter_id;
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u_int8_t parameter_size_bytes;
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u_int8_t data[1];
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} TWE_Param __attribute__ ((packed));
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/* response queue entry */
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typedef union
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{
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struct
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{
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u_int32_t undefined_1:4;
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u_int32_t response_id:8;
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u_int32_t undefined_2:20;
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} u;
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u_int32_t value;
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} TWE_Response_Queue;
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#if 0 /* no idea what these will be useful for yet */
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typedef struct
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{
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int32_t buffer;
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u_int8_t opcode;
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u_int16_t table_id;
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u_int8_t parameter_id;
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u_int8_t parameter_size_bytes;
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u_int8_t data[1];
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} TWE_Ioctl __attribute__ ((packed));
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typedef struct
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{
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u_int32_t base_addr;
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u_int32_t control_reg_addr;
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u_int32_t status_reg_addr;
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u_int32_t command_que_addr;
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u_int32_t response_que_addr;
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} TWE_Registers __attribute__ ((packed));
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typedef struct
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{
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char *buffer;
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int32_t length;
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int32_t offset;
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int32_t position;
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} TWE_Info __attribute__ ((packed));
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#endif
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