8ea4ab29a0
am now able to run 32 cores ok.. but I still will hang on buildworld with a NFS problem. I suspect I am missing a patch for the netlogic rge driver. JC check and see if I am missing anything except your core-mask changes Obtained from: JC
297 lines
12 KiB
C
297 lines
12 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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* __FBSDID("$FreeBSD$");
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*
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* RMI_BSD */
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#ifndef _RMI_PIC_H_
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#define _RMI_PIC_H_
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#include <sys/cdefs.h>
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extern int rmi_spin_mutex_safe;
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <mips/rmi/iomap.h>
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#define PIC_IRT_WD_INDEX 0
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#define PIC_IRT_TIMER_0_INDEX 1
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#define PIC_IRT_TIMER_1_INDEX 2
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#define PIC_IRT_TIMER_2_INDEX 3
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#define PIC_IRT_TIMER_3_INDEX 4
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#define PIC_IRT_TIMER_4_INDEX 5
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#define PIC_IRT_TIMER_5_INDEX 6
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#define PIC_IRT_TIMER_6_INDEX 7
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#define PIC_IRT_TIMER_7_INDEX 8
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#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
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#define PIC_IRT_UART_0_INDEX 9
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#define PIC_IRT_UART_1_INDEX 10
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#define PIC_IRT_I2C_0_INDEX 11
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#define PIC_IRT_I2C_1_INDEX 12
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#define PIC_IRT_PCMCIA_INDEX 13
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#define PIC_IRT_GPIO_INDEX 14
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#define PIC_IRT_HYPER_INDEX 15
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#define PIC_IRT_PCIX_INDEX 16
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#define PIC_IRT_GMAC0_INDEX 17
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#define PIC_IRT_GMAC1_INDEX 18
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#define PIC_IRT_GMAC2_INDEX 19
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#define PIC_IRT_GMAC3_INDEX 20
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#define PIC_IRT_XGS0_INDEX 21
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#define PIC_IRT_XGS1_INDEX 22
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#define PIC_IRT_HYPER_FATAL_INDEX 23
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#define PIC_IRT_PCIX_FATAL_INDEX 24
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#define PIC_IRT_BRIDGE_AERR_INDEX 25
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#define PIC_IRT_BRIDGE_BERR_INDEX 26
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#define PIC_IRT_BRIDGE_TB_INDEX 27
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#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
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/* numbering for XLS */
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#define PIC_IRT_BRIDGE_ERR_INDEX 25
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#define PIC_IRT_PCIE_LINK0_INDEX 26
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#define PIC_IRT_PCIE_LINK1_INDEX 27
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#define PIC_IRT_PCIE_LINK2_INDEX 23
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#define PIC_IRT_PCIE_LINK3_INDEX 24
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#define PIC_IRT_PCIE_INT_INDEX 28
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#define PIC_IRT_PCIE_FATAL_INDEX 29
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#define PIC_IRT_GPIO_B_INDEX 30
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#define PIC_IRT_USB_INDEX 31
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#define PIC_NUM_IRTS 32
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#define PIC_SYS_TIMER_MAXVAL_0_BASE 0x100
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#define PIC_SYS_TIMER_MAXVAL_1_BASE 0x110
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#define PIC_SYS_TIMER_0_BASE 0x120
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#define PIC_SYS_TIMER_1_BASE 0x130
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#define PIC_CLOCK_TIMER 7
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#define PIC_CTRL 0x00
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#define PIC_IPI 0x04
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#define PIC_INT_ACK 0x06
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#define WD_MAX_VAL_0 0x08
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#define WD_MAX_VAL_1 0x09
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#define WD_MASK_0 0x0a
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#define WD_MASK_1 0x0b
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#define WD_HEARBEAT_0 0x0c
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#define WD_HEARBEAT_1 0x0d
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#define PIC_IRT_0_BASE 0x40
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#define PIC_IRT_1_BASE 0x80
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#define PIC_IRT_0_WD (PIC_IRT_0_BASE + PIC_IRT_WD_INDEX)
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#define PIC_IRT_1_WD (PIC_IRT_1_BASE + PIC_IRT_WD_INDEX)
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#define PIC_IRT_0_TIMER_0 (PIC_IRT_0_BASE + PIC_IRT_TIMER_0_INDEX)
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#define PIC_IRT_1_TIMER_0 (PIC_IRT_1_BASE + PIC_IRT_TIMER_0_INDEX)
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#define PIC_IRT_0_TIMER_1 (PIC_IRT_0_BASE + PIC_IRT_TIMER_1_INDEX)
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#define PIC_IRT_1_TIMER_1 (PIC_IRT_1_BASE + PIC_IRT_TIMER_1_INDEX)
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#define PIC_IRT_0_TIMER_2 (PIC_IRT_0_BASE + PIC_IRT_TIMER_2_INDEX)
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#define PIC_IRT_1_TIMER_2 (PIC_IRT_1_BASE + PIC_IRT_TIMER_2_INDEX)
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#define PIC_IRT_0_TIMER_3 (PIC_IRT_0_BASE + PIC_IRT_TIMER_3_INDEX)
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#define PIC_IRT_1_TIMER_3 (PIC_IRT_1_BASE + PIC_IRT_TIMER_3_INDEX)
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#define PIC_IRT_0_TIMER_4 (PIC_IRT_0_BASE + PIC_IRT_TIMER_4_INDEX)
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#define PIC_IRT_1_TIMER_4 (PIC_IRT_1_BASE + PIC_IRT_TIMER_4_INDEX)
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#define PIC_IRT_0_TIMER_5 (PIC_IRT_0_BASE + PIC_IRT_TIMER_5_INDEX)
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#define PIC_IRT_1_TIMER_5 (PIC_IRT_1_BASE + PIC_IRT_TIMER_5_INDEX)
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#define PIC_IRT_0_TIMER_6 (PIC_IRT_0_BASE + PIC_IRT_TIMER_6_INDEX)
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#define PIC_IRT_1_TIMER_6 (PIC_IRT_1_BASE + PIC_IRT_TIMER_6_INDEX)
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#define PIC_IRT_0_TIMER_7 (PIC_IRT_0_BASE + PIC_IRT_TIMER_7_INDEX)
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#define PIC_IRT_1_TIMER_7 (PIC_IRT_1_BASE + PIC_IRT_TIMER_7_INDEX)
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#define PIC_IRT_0_CLOCK (PIC_IRT_0_TIMER_7)
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#define PIC_IRT_1_CLOCK (PIC_IRT_1_TIMER_7)
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#define PIC_IRT_0_UART_0 (PIC_IRT_0_BASE + PIC_IRT_UART_0_INDEX)
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#define PIC_IRT_1_UART_0 (PIC_IRT_1_BASE + PIC_IRT_UART_0_INDEX)
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#define PIC_IRT_0_UART_1 (PIC_IRT_0_BASE + PIC_IRT_UART_1_INDEX)
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#define PIC_IRT_1_UART_1 (PIC_IRT_1_BASE + PIC_IRT_UART_1_INDEX)
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#define PIC_IRT_0_I2C_0 (PIC_IRT_0_BASE + PIC_IRT_I2C_0_INDEX)
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#define PIC_IRT_1_I2C_0 (PIC_IRT_1_BASE + PIC_IRT_I2C_0_INDEX)
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#define PIC_IRT_0_I2C_1 (PIC_IRT_0_BASE + PIC_IRT_I2C_1_INDEX)
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#define PIC_IRT_1_I2C_1 (PIC_IRT_1_BASE + PIC_IRT_I2C_1_INDEX)
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#define PIC_IRT_0_HYPER (PIC_IRT_0_BASE + PIC_IRT_HYPER_INDEX)
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#define PIC_IRT_1_HYPER (PIC_IRT_1_BASE + PIC_IRT_HYPER_INDEX)
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#define PIC_IRT_0_PCIX (PIC_IRT_0_BASE + PIC_IRT_PCIX_INDEX)
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#define PIC_IRT_1_PCIX (PIC_IRT_1_BASE + PIC_IRT_PCIX_INDEX)
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#define PIC_TIMER_0_MAXVAL_0 (PIC_SYS_TIMER_MAXVAL_0_BASE + 0)
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#define PIC_TIMER_0_MAXVAL_1 (PIC_SYS_TIMER_MAXVAL_1_BASE + 0)
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#define PIC_TIMER_0_COUNTER_0 (PIC_SYS_TIMER_0_BASE + 0)
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#define PIC_TIMER_0_COUNTER_1 (PIC_SYS_TIMER_1_BASE + 0)
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#define PIC_TIMER_6_MAXVAL_0 (PIC_SYS_TIMER_MAXVAL_0_BASE + 6)
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#define PIC_TIMER_6_MAXVAL_1 (PIC_SYS_TIMER_MAXVAL_1_BASE + 6)
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#define PIC_TIMER_6_COUNTER_0 (PIC_SYS_TIMER_0_BASE + 6)
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#define PIC_TIMER_6_COUNTER_1 (PIC_SYS_TIMER_1_BASE + 6)
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#define PIC_TIMER_7_MAXVAL_0 (PIC_SYS_TIMER_MAXVAL_0_BASE + 7)
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#define PIC_TIMER_7_MAXVAL_1 (PIC_SYS_TIMER_MAXVAL_1_BASE + 7)
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#define PIC_TIMER_7_COUNTER_0 (PIC_SYS_TIMER_0_BASE + 7)
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#define PIC_TIMER_7_COUNTER_1 (PIC_SYS_TIMER_1_BASE + 7)
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#define PIC_IRQ_BASE 8
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#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
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#define PIC_WD_IRQ (PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
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#define PIC_TIMER_0_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_0_INDEX)
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#define PIC_TIMER_1_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_1_INDEX)
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#define PIC_TIMER_2_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_2_INDEX)
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#define PIC_TIMER_3_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_3_INDEX)
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#define PIC_TIMER_4_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_4_INDEX)
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#define PIC_TIMER_5_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_5_INDEX)
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#define PIC_TIMER_6_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_6_INDEX)
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#define PIC_TIMER_7_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_7_INDEX)
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#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ)
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#define PIC_UART_0_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX)
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#define PIC_UART_1_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX)
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#define PIC_I2C_0_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX)
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#define PIC_I2C_1_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX)
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#define PIC_PCMCIA_IRQ (PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX)
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#define PIC_GPIO_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX)
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#define PIC_HYPER_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX)
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#define PIC_PCIX_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX)
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#define PIC_GMAC_0_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX)
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#define PIC_GMAC_1_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX)
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#define PIC_GMAC_2_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX)
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#define PIC_GMAC_3_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX)
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#define PIC_XGS_0_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX)
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#define PIC_XGS_1_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX)
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#define PIC_HYPER_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX)
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#define PIC_PCIX_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX)
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#define PIC_BRIDGE_AERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX)
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#define PIC_BRIDGE_BERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
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#define PIC_BRIDGE_TB_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
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#define PIC_BRIDGE_AERR_NMI_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
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#define PIC_BRIDGE_ERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
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#define PIC_PCIE_LINK0_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
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#define PIC_PCIE_LINK1_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
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#define PIC_PCIE_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX)
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#define PIC_PCIE_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX)
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#define PIC_PCIE_INT_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_INT__INDEX)
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#define PIC_PCIE_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX)
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#define PIC_GPIO_B_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
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#define PIC_USB_IRQ (PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
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#define PIC_IRT_LAST_IRQ PIC_USB_IRQ
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#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) ( ((irq)>=PIC_TIMER_0_IRQ) && ((irq)<=PIC_TIMER_7_IRQ) )
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#define PIC_IRQ_IS_IRT(irq) ( ((irq)>=PIC_IRT_FIRST_IRQ) && ((irq)<=PIC_IRT_LAST_IRQ) )
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extern struct mtx xlr_pic_lock;
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static __inline__ __uint32_t
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pic_read_control(int haslock)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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__uint32_t reg;
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_lock_spin(&xlr_pic_lock);
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xlr_read_reg(mmio, PIC_CTRL);
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_unlock_spin(&xlr_pic_lock);
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return reg;
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}
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static __inline__ void
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pic_write_control(__uint32_t control, int haslock)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_CTRL, control);
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_unlock_spin(&xlr_pic_lock);
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}
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static __inline__ void
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pic_update_control(__uint32_t control, int haslock)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_unlock_spin(&xlr_pic_lock);
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}
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static __inline__ void
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pic_ack(int irq, int haslock)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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/* ack the pic, if needed */
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if (!PIC_IRQ_IS_IRT(irq))
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return;
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if (PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_unlock_spin(&xlr_pic_lock);
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return;
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}
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return;
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}
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static inline void
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pic_delayed_ack(int irq, int haslock)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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if (!PIC_IRQ_IS_IRT(irq))
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return;
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if (!PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
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if ((rmi_spin_mutex_safe)&& (haslock == 0))
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
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if ((rmi_spin_mutex_safe) && (haslock == 0))
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mtx_unlock_spin(&xlr_pic_lock);
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return;
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}
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}
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static inline
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void pic_send_ipi(int cpu, int ipi, int haslock)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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int tid, pid;
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tid = cpu & 0x3;
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pid = (cpu >> 2) & 0x7;
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xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi);
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}
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#endif /* _RMI_PIC_H_ */
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