ac2fffa4b7
Uses of mallocarray(9). The use of mallocarray(9) has rocketed the required swap to build FreeBSD. This is likely caused by the allocation size attributes which put extra pressure on the compiler. Given that most of these checks are superfluous we have to choose better where to use mallocarray(9). We still have more uses of mallocarray(9) but hopefully this is enough to bring swap usage to a reasonable level. Reported by: wosch PR: 225197
508 lines
16 KiB
C
508 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (c) Comtrol Corporation <support@comtrol.com>
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* All rights reserved.
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*
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* ISA-specific part separated from:
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* sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted prodived that the follwoing conditions
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* are met.
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* 1. Redistributions of source code must retain the above copyright
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* notive, this list of conditions and the following disclainer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials prodided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Comtrol Corporation.
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* 4. The name of Comtrol Corporation may not be used to endorse or
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* promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/fcntl.h>
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#include <sys/malloc.h>
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#include <sys/tty.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#define ROCKET_C
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#include <dev/rp/rpreg.h>
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#include <dev/rp/rpvar.h>
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#include <isa/isavar.h>
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/* ISA-specific part of CONTROLLER_t */
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struct ISACONTROLLER_T {
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int MBaseIO; /* rid of the Mudbac controller for this controller */
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int MReg0IO; /* offset0 of the Mudbac controller for this controller */
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int MReg1IO; /* offset1 of the Mudbac controller for this controller */
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int MReg2IO; /* offset2 of the Mudbac controller for this controller */
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int MReg3IO; /* offset3 of the Mudbac controller for this controller */
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Byte_t MReg2;
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Byte_t MReg3;
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};
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typedef struct ISACONTROLLER_T ISACONTROLLER_t;
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#define ISACTL(ctlp) ((ISACONTROLLER_t *)((ctlp)->bus_ctlp))
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/***************************************************************************
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Function: sControllerEOI
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Purpose: Strobe the MUDBAC's End Of Interrupt bit.
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Call: sControllerEOI(MudbacCtlP,CtlP)
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CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
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CONTROLLER_T *CtlP; Ptr to controller structure
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*/
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#define sControllerEOI(MudbacCtlP,CtlP) \
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rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg2IO,ISACTL(CtlP)->MReg2 | INT_STROB)
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/***************************************************************************
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Function: sDisAiop
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Purpose: Disable I/O access to an AIOP
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Call: sDisAiop(MudbacCtlP,CtlP)
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CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
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CONTROLLER_T *CtlP; Ptr to controller structure
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int AiopNum; Number of AIOP on controller
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*/
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#define sDisAiop(MudbacCtlP,CtlP,AIOPNUM) \
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{ \
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ISACTL(CtlP)->MReg3 &= rp_sBitMapClrTbl[AIOPNUM]; \
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rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3); \
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}
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/***************************************************************************
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Function: sEnAiop
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Purpose: Enable I/O access to an AIOP
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Call: sEnAiop(MudbacCtlP,CtlP)
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CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
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CONTROLLER_T *CtlP; Ptr to controller structure
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int AiopNum; Number of AIOP on controller
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*/
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#define sEnAiop(MudbacCtlP,CtlP,AIOPNUM) \
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{ \
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ISACTL(CtlP)->MReg3 |= rp_sBitMapSetTbl[AIOPNUM]; \
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rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3); \
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}
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/***************************************************************************
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Function: sGetControllerIntStatus
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Purpose: Get the controller interrupt status
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Call: sGetControllerIntStatus(MudbacCtlP,CtlP)
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CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
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CONTROLLER_T *CtlP; Ptr to controller structure
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Return: Byte_t: The controller interrupt status in the lower 4
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bits. Bits 0 through 3 represent AIOP's 0
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through 3 respectively. If a bit is set that
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AIOP is interrupting. Bits 4 through 7 will
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always be cleared.
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*/
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#define sGetControllerIntStatus(MudbacCtlP,CtlP) \
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(rp_readio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg1IO) & 0x0f)
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static devclass_t rp_devclass;
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static CONTROLLER_t *rp_controller;
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static int rp_nisadevs;
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static int rp_probe(device_t dev);
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static int rp_attach(device_t dev);
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static void rp_isareleaseresource(CONTROLLER_t *ctlp);
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static int sInitController(CONTROLLER_T *CtlP,
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CONTROLLER_T *MudbacCtlP,
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int AiopNum,
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int IRQNum,
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Byte_t Frequency,
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int PeriodicOnly);
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static rp_aiop2rid_t rp_isa_aiop2rid;
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static rp_aiop2off_t rp_isa_aiop2off;
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static rp_ctlmask_t rp_isa_ctlmask;
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static int
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rp_probe(device_t dev)
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{
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int unit;
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CONTROLLER_t *controller;
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int num_aiops;
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CONTROLLER_t *ctlp;
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int retval;
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/*
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* We have no PnP RocketPort cards.
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* (At least according to LINT)
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*/
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if (isa_get_logicalid(dev) != 0)
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return (ENXIO);
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/* We need IO port resource to configure an ISA device. */
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if (bus_get_resource_count(dev, SYS_RES_IOPORT, 0) == 0)
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return (ENXIO);
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unit = device_get_unit(dev);
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if (unit >= 4) {
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device_printf(dev, "rpprobe: unit number %d invalid.\n", unit);
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return (ENXIO);
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}
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device_printf(dev, "probing for RocketPort(ISA) unit %d.\n", unit);
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ctlp = device_get_softc(dev);
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bzero(ctlp, sizeof(*ctlp));
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ctlp->dev = dev;
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ctlp->aiop2rid = rp_isa_aiop2rid;
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ctlp->aiop2off = rp_isa_aiop2off;
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ctlp->ctlmask = rp_isa_ctlmask;
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/* The IO ports of AIOPs for an ISA controller are discrete. */
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ctlp->io_num = 1;
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ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * MAX_AIOPS_PER_BOARD, M_DEVBUF, M_NOWAIT | M_ZERO);
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ctlp->io = malloc(sizeof(*(ctlp->io)) * MAX_AIOPS_PER_BOARD, M_DEVBUF, M_NOWAIT | M_ZERO);
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if (ctlp->io_rid == NULL || ctlp->io == NULL) {
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device_printf(dev, "rp_attach: Out of memory.\n");
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retval = ENOMEM;
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goto nogo;
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}
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ctlp->bus_ctlp = malloc(sizeof(ISACONTROLLER_t) * 1, M_DEVBUF, M_NOWAIT | M_ZERO);
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if (ctlp->bus_ctlp == NULL) {
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device_printf(dev, "rp_attach: Out of memory.\n");
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retval = ENOMEM;
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goto nogo;
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}
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ctlp->io_rid[0] = 0;
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if (rp_controller != NULL) {
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controller = rp_controller;
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ctlp->io[0] = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0x40, RF_ACTIVE);
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} else {
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controller = rp_controller = ctlp;
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ctlp->io[0] = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0x44, RF_ACTIVE);
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}
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if (ctlp->io[0] == NULL) {
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device_printf(dev, "rp_attach: Resource not available.\n");
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retval = ENXIO;
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goto nogo;
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}
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num_aiops = sInitController(ctlp,
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controller,
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MAX_AIOPS_PER_BOARD, 0,
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FREQ_DIS, 0);
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if (num_aiops <= 0) {
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device_printf(dev, "board%d init failed.\n", unit);
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retval = ENXIO;
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goto nogo;
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}
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if (rp_controller == NULL)
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rp_controller = controller;
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rp_nisadevs++;
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device_set_desc(dev, "RocketPort ISA");
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return (0);
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nogo:
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rp_isareleaseresource(ctlp);
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return (retval);
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}
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static int
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rp_attach(device_t dev)
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{
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int unit;
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int num_ports, num_aiops;
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int aiop;
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CONTROLLER_t *ctlp;
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int retval;
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unit = device_get_unit(dev);
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ctlp = device_get_softc(dev);
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#ifdef notdef
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num_aiops = sInitController(ctlp,
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rp_controller,
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MAX_AIOPS_PER_BOARD, 0,
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FREQ_DIS, 0);
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#else
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num_aiops = ctlp->NumAiop;
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#endif /* notdef */
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num_ports = 0;
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for(aiop=0; aiop < num_aiops; aiop++) {
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sResetAiopByNum(ctlp, aiop);
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sEnAiop(rp_controller, ctlp, aiop);
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num_ports += sGetAiopNumChan(ctlp, aiop);
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}
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retval = rp_attachcommon(ctlp, num_aiops, num_ports);
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if (retval != 0)
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goto nogo;
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return (0);
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nogo:
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rp_isareleaseresource(ctlp);
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return (retval);
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}
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static void
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rp_isareleaseresource(CONTROLLER_t *ctlp)
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{
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int i;
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rp_releaseresource(ctlp);
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if (ctlp == rp_controller)
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rp_controller = NULL;
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if (ctlp->io != NULL) {
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for (i = 0 ; i < MAX_AIOPS_PER_BOARD ; i++)
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if (ctlp->io[i] != NULL)
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bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[i], ctlp->io[i]);
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free(ctlp->io, M_DEVBUF);
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}
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if (ctlp->io_rid != NULL)
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free(ctlp->io_rid, M_DEVBUF);
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if (rp_controller != NULL && rp_controller->io[ISACTL(ctlp)->MBaseIO] != NULL) {
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bus_release_resource(rp_controller->dev, SYS_RES_IOPORT, rp_controller->io_rid[ISACTL(ctlp)->MBaseIO], rp_controller->io[ISACTL(ctlp)->MBaseIO]);
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rp_controller->io[ISACTL(ctlp)->MBaseIO] = NULL;
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rp_controller->io_rid[ISACTL(ctlp)->MBaseIO] = 0;
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}
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if (ctlp->bus_ctlp != NULL)
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free(ctlp->bus_ctlp, M_DEVBUF);
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}
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/***************************************************************************
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Function: sInitController
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Purpose: Initialization of controller global registers and controller
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structure.
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Call: sInitController(CtlP,MudbacCtlP,AiopNum,
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IRQNum,Frequency,PeriodicOnly)
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CONTROLLER_T *CtlP; Ptr to controller structure
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CONTROLLER_T *MudbacCtlP; Ptr to Mudbac controller structure
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int AiopNum; Number of Aiops
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int IRQNum; Interrupt Request number. Can be any of the following:
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0: Disable global interrupts
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3: IRQ 3
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4: IRQ 4
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5: IRQ 5
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9: IRQ 9
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10: IRQ 10
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11: IRQ 11
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12: IRQ 12
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15: IRQ 15
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Byte_t Frequency: A flag identifying the frequency
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of the periodic interrupt, can be any one of the following:
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FREQ_DIS - periodic interrupt disabled
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FREQ_137HZ - 137 Hertz
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FREQ_69HZ - 69 Hertz
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FREQ_34HZ - 34 Hertz
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FREQ_17HZ - 17 Hertz
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FREQ_9HZ - 9 Hertz
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FREQ_4HZ - 4 Hertz
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If IRQNum is set to 0 the Frequency parameter is
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overidden, it is forced to a value of FREQ_DIS.
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int PeriodicOnly: TRUE if all interrupts except the periodic
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interrupt are to be blocked.
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FALSE is both the periodic interrupt and
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other channel interrupts are allowed.
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If IRQNum is set to 0 the PeriodicOnly parameter is
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overidden, it is forced to a value of FALSE.
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Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
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initialization failed.
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Comments:
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If periodic interrupts are to be disabled but AIOP interrupts
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are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE.
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If interrupts are to be completely disabled set IRQNum to 0.
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Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an
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invalid combination.
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This function performs initialization of global interrupt modes,
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but it does not actually enable global interrupts. To enable
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and disable global interrupts use functions sEnGlobalInt() and
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sDisGlobalInt(). Enabling of global interrupts is normally not
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done until all other initializations are complete.
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Even if interrupts are globally enabled, they must also be
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individually enabled for each channel that is to generate
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interrupts.
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Warnings: No range checking on any of the parameters is done.
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No context switches are allowed while executing this function.
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After this function all AIOPs on the controller are disabled,
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they can be enabled with sEnAiop().
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*/
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static int
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sInitController( CONTROLLER_T *CtlP,
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CONTROLLER_T *MudbacCtlP,
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int AiopNum,
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int IRQNum,
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Byte_t Frequency,
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int PeriodicOnly)
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{
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int i;
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int ctl_base, aiop_base, aiop_size;
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CtlP->CtlID = CTLID_0001; /* controller release 1 */
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ISACTL(CtlP)->MBaseIO = rp_nisadevs;
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if (MudbacCtlP->io[ISACTL(CtlP)->MBaseIO] != NULL) {
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ISACTL(CtlP)->MReg0IO = 0x40 + 0;
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ISACTL(CtlP)->MReg1IO = 0x40 + 1;
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ISACTL(CtlP)->MReg2IO = 0x40 + 2;
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ISACTL(CtlP)->MReg3IO = 0x40 + 3;
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} else {
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MudbacCtlP->io_rid[ISACTL(CtlP)->MBaseIO] = ISACTL(CtlP)->MBaseIO;
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ctl_base = rman_get_start(MudbacCtlP->io[0]) + 0x40 + 0x400 * rp_nisadevs;
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MudbacCtlP->io[ISACTL(CtlP)->MBaseIO] = bus_alloc_resource(MudbacCtlP->dev, SYS_RES_IOPORT, &CtlP->io_rid[ISACTL(CtlP)->MBaseIO], ctl_base, ctl_base + 3, 4, RF_ACTIVE);
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ISACTL(CtlP)->MReg0IO = 0;
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ISACTL(CtlP)->MReg1IO = 1;
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ISACTL(CtlP)->MReg2IO = 2;
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ISACTL(CtlP)->MReg3IO = 3;
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}
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#if 1
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ISACTL(CtlP)->MReg2 = 0; /* interrupt disable */
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ISACTL(CtlP)->MReg3 = 0; /* no periodic interrupts */
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#else
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if(sIRQMap[IRQNum] == 0) /* interrupts globally disabled */
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{
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ISACTL(CtlP)->MReg2 = 0; /* interrupt disable */
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ISACTL(CtlP)->MReg3 = 0; /* no periodic interrupts */
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}
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else
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{
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ISACTL(CtlP)->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
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ISACTL(CtlP)->MReg3 = Frequency; /* set frequency */
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if(PeriodicOnly) /* periodic interrupt only */
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{
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ISACTL(CtlP)->MReg3 |= PERIODIC_ONLY;
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}
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}
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#endif
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rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg2IO,ISACTL(CtlP)->MReg2);
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rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,ISACTL(CtlP)->MReg3IO,ISACTL(CtlP)->MReg3);
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sControllerEOI(MudbacCtlP,CtlP); /* clear EOI if warm init */
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/* Init AIOPs */
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CtlP->NumAiop = 0;
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for(i=0; i < AiopNum; i++)
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{
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if (CtlP->io[i] == NULL) {
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CtlP->io_rid[i] = i;
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aiop_base = rman_get_start(CtlP->io[0]) + 0x400 * i;
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if (rp_nisadevs == 0)
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aiop_size = 0x44;
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else
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aiop_size = 0x40;
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CtlP->io[i] = bus_alloc_resource(CtlP->dev, SYS_RES_IOPORT, &CtlP->io_rid[i], aiop_base, aiop_base + aiop_size - 1, aiop_size, RF_ACTIVE);
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} else
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aiop_base = rman_get_start(CtlP->io[i]);
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rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,
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ISACTL(CtlP)->MReg2IO,
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ISACTL(CtlP)->MReg2 | (i & 0x03)); /* AIOP index */
|
|
rp_writeio1(MudbacCtlP,ISACTL(CtlP)->MBaseIO,
|
|
ISACTL(CtlP)->MReg0IO,
|
|
(Byte_t)(aiop_base >> 6)); /* set up AIOP I/O in MUDBAC */
|
|
sEnAiop(MudbacCtlP,CtlP,i); /* enable the AIOP */
|
|
|
|
CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
|
|
if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
|
|
{
|
|
sDisAiop(MudbacCtlP,CtlP,i); /* disable AIOP */
|
|
bus_release_resource(CtlP->dev, SYS_RES_IOPORT, CtlP->io_rid[i], CtlP->io[i]);
|
|
CtlP->io[i] = NULL;
|
|
break; /* done looking for AIOPs */
|
|
}
|
|
|
|
CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i); /* num channels in AIOP */
|
|
rp_writeaiop2(CtlP,i,_INDX_ADDR,_CLK_PRE); /* clock prescaler */
|
|
rp_writeaiop1(CtlP,i,_INDX_DATA,CLOCK_PRESC);
|
|
CtlP->NumAiop++; /* bump count of AIOPs */
|
|
sDisAiop(MudbacCtlP,CtlP,i); /* disable AIOP */
|
|
}
|
|
|
|
if(CtlP->NumAiop == 0)
|
|
return(-1);
|
|
else
|
|
return(CtlP->NumAiop);
|
|
}
|
|
|
|
/*
|
|
* ARGSUSED
|
|
* Maps (aiop, offset) to rid.
|
|
*/
|
|
static int
|
|
rp_isa_aiop2rid(int aiop, int offset)
|
|
{
|
|
/* rid equals to aiop for an ISA controller. */
|
|
return aiop;
|
|
}
|
|
|
|
/*
|
|
* ARGSUSED
|
|
* Maps (aiop, offset) to the offset of resource.
|
|
*/
|
|
static int
|
|
rp_isa_aiop2off(int aiop, int offset)
|
|
{
|
|
/* Each aiop has its own resource. */
|
|
return offset;
|
|
}
|
|
|
|
/* Read the int status for an ISA controller. */
|
|
static unsigned char
|
|
rp_isa_ctlmask(CONTROLLER_t *ctlp)
|
|
{
|
|
return sGetControllerIntStatus(rp_controller,ctlp);
|
|
}
|
|
|
|
static device_method_t rp_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, rp_probe),
|
|
DEVMETHOD(device_attach, rp_attach),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t rp_driver = {
|
|
"rp",
|
|
rp_methods,
|
|
sizeof(CONTROLLER_t),
|
|
};
|
|
|
|
/*
|
|
* rp can be attached to an isa bus.
|
|
*/
|
|
DRIVER_MODULE(rp, isa, rp_driver, rp_devclass, 0, 0);
|