436 lines
11 KiB
Plaintext
436 lines
11 KiB
Plaintext
/*
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* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this file; if not, write to the Free
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* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include "armv7-m.dtsi"
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#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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};
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soc {
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timer2: timer@40000000 {
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compatible = "st,stm32-timer";
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reg = <0x40000000 0x400>;
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interrupts = <28>;
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clocks = <&rcc 0 128>;
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status = "disabled";
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};
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timer3: timer@40000400 {
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compatible = "st,stm32-timer";
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reg = <0x40000400 0x400>;
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interrupts = <29>;
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clocks = <&rcc 0 129>;
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status = "disabled";
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};
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timer4: timer@40000800 {
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compatible = "st,stm32-timer";
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reg = <0x40000800 0x400>;
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interrupts = <30>;
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clocks = <&rcc 0 130>;
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status = "disabled";
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};
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&rcc 0 131>;
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};
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timer6: timer@40001000 {
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compatible = "st,stm32-timer";
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reg = <0x40001000 0x400>;
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interrupts = <54>;
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clocks = <&rcc 0 132>;
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status = "disabled";
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};
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timer7: timer@40001400 {
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compatible = "st,stm32-timer";
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reg = <0x40001400 0x400>;
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interrupts = <55>;
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clocks = <&rcc 0 133>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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interrupts = <38>;
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clocks = <&rcc 0 145>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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interrupts = <39>;
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clocks = <&rcc 0 146>;
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status = "disabled";
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dmas = <&dma1 1 4 0x400 0x0>,
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<&dma1 3 4 0x400 0x0>;
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dma-names = "rx", "tx";
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};
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usart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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interrupts = <52>;
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clocks = <&rcc 0 147>;
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status = "disabled";
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};
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usart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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interrupts = <53>;
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clocks = <&rcc 0 148>;
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status = "disabled";
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};
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usart7: serial@40007800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40007800 0x400>;
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interrupts = <82>;
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clocks = <&rcc 0 158>;
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status = "disabled";
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};
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usart8: serial@40007c00 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40007c00 0x400>;
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interrupts = <83>;
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clocks = <&rcc 0 159>;
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status = "disabled";
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};
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usart1: serial@40011000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011000 0x400>;
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interrupts = <37>;
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clocks = <&rcc 0 164>;
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status = "disabled";
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dmas = <&dma2 2 4 0x400 0x0>,
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<&dma2 7 4 0x400 0x0>;
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dma-names = "rx", "tx";
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};
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usart6: serial@40011400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011400 0x400>;
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interrupts = <71>;
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clocks = <&rcc 0 165>;
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status = "disabled";
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};
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syscfg: system-config@40013800 {
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compatible = "syscon";
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reg = <0x40013800 0x400>;
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};
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exti: interrupt-controller@40013c00 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x40013C00 0x400>;
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interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
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};
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pwrcfg: power-config@40007000 {
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compatible = "syscon";
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reg = <0x40007000 0x400>;
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};
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pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32f429-pinctrl";
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ranges = <0 0x40020000 0x3000>;
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interrupt-parent = <&exti>;
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st,syscfg = <&syscfg 0x8>;
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pins-are-numbered;
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gpioa: gpio@40020000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc 0 0>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@40020400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x400 0x400>;
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clocks = <&rcc 0 1>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@40020800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x800 0x400>;
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clocks = <&rcc 0 2>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@40020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0xc00 0x400>;
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clocks = <&rcc 0 3>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@40021000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc 0 4>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@40021400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1400 0x400>;
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clocks = <&rcc 0 5>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@40021800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1800 0x400>;
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clocks = <&rcc 0 6>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@40021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1c00 0x400>;
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clocks = <&rcc 0 7>;
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st,bank-name = "GPIOH";
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};
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gpioi: gpio@40022000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc 0 8>;
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st,bank-name = "GPIOI";
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};
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gpioj: gpio@40022400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x2400 0x400>;
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clocks = <&rcc 0 9>;
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st,bank-name = "GPIOJ";
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};
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gpiok: gpio@40022800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x2800 0x400>;
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clocks = <&rcc 0 10>;
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st,bank-name = "GPIOK";
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};
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
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bias-disable;
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};
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};
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usbotg_hs_pins_a: usbotg_hs@0 {
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pins {
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pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
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<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
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<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
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<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
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<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
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<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
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<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
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<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
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<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
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<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
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<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
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<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
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<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
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<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
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<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
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<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
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<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
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<STM32F429_PA2_FUNC_ETH_MDIO>,
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<STM32F429_PC1_FUNC_ETH_MDC>,
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<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
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<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
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<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
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<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
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<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
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<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
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slew-rate = <2>;
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};
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};
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};
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rcc: rcc@40023810 {
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#reset-cells = <1>;
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#clock-cells = <2>;
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compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
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reg = <0x40023800 0x400>;
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clocks = <&clk_hse>;
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st,syscfg = <&pwrcfg>;
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};
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dma1: dma-controller@40026000 {
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compatible = "st,stm32-dma";
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reg = <0x40026000 0x400>;
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interrupts = <11>,
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<12>,
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<13>,
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<14>,
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<15>,
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<16>,
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<17>,
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<47>;
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clocks = <&rcc 0 21>;
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#dma-cells = <4>;
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};
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dma2: dma-controller@40026400 {
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compatible = "st,stm32-dma";
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reg = <0x40026400 0x400>;
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interrupts = <56>,
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<57>,
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<58>,
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<59>,
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<60>,
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<68>,
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<69>,
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<70>;
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clocks = <&rcc 0 22>;
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#dma-cells = <4>;
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st,mem2mem;
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};
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mac: ethernet@40028000 {
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compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
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reg = <0x40028000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <61>;
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interrupt-names = "macirq";
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clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
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clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
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st,syscon = <&syscfg 0x4>;
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snps,pbl = <8>;
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snps,mixed-burst;
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status = "disabled";
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};
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usbotg_hs: usb@40040000 {
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compatible = "snps,dwc2";
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reg = <0x40040000 0x40000>;
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interrupts = <77>;
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clocks = <&rcc 0 29>;
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clock-names = "otg";
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status = "disabled";
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};
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rng: rng@50060800 {
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compatible = "st,stm32-rng";
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reg = <0x50060800 0x400>;
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interrupts = <80>;
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clocks = <&rcc 0 38>;
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};
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};
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};
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&systick {
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clocks = <&rcc 1 0>;
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status = "okay";
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};
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