d580860e12
Features: Jumbo frames (up to 9600), LRO (Large Receive Offload),
TSO (TCP segmentation offload), RTH (Receive Traffic Hash).
Submitted by: Sriram Rapuru at Exar
MFC after: 2 weeks
224 lines
8.0 KiB
C
224 lines
8.0 KiB
C
/*-
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* Copyright(c) 2002-2011 Exar Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification are permitted provided the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Exar Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef VXGE_HAL_FIFO_H
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#define VXGE_HAL_FIFO_H
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__EXTERN_BEGIN_DECLS
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/*
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* struct __hal_fifo_t - Fifo.
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* @channel: Channel "base" of this fifo, the common part of all HAL
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* channels.
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* @mempool: Memory pool, from which descriptors get allocated.
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* @config: Fifo configuration, part of device configuration
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* (see vxge_hal_device_config_t {}).
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* @interrupt_type: Interrupt type to be used
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* @no_snoop_bits: See vxge_hal_fifo_config_t {}.
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* @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
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* bytes. Setting @memblock_size to page size ensures
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* by-page allocation of descriptors. 128K bytes is the
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* maximum supported block size.
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* @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
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* on TxDL please refer to X3100 UG.
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* @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
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* per-TxDL HAL private space (__hal_fifo_txdl_priv_t).
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* @txdl_priv_size: Per-TxDL space reserved for HAL and ULD
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* @per_txdl_space: Per txdl private space for the ULD
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* @txdlblock_priv_size: Total private space per TXDL memory block
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* @align_size: Cache alignment size
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* @callback: Fifo completion callback. HAL invokes the callback when there
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* are new completions on that fifo. In many implementations
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* the @callback executes in the hw interrupt context.
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* @txdl_init: Fifo's descriptor-initialize callback.
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* See vxge_hal_fifo_txdl_init_f {}.
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* If not NULL, HAL invokes the callback when opening
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* the fifo via vxge_hal_vpath_open().
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* @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
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* HAL invokes the callback when closing the corresponding fifo.
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* See also vxge_hal_fifo_txdl_term_f {}.
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* @stats: Statistics of this fifo
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*
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* Fifo channel.
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* Note: The structure is cache line aligned.
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*/
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typedef struct __hal_fifo_t {
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__hal_channel_t channel;
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vxge_hal_mempool_t *mempool;
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vxge_hal_fifo_config_t *config;
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u64 interrupt_type;
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u32 no_snoop_bits;
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u32 memblock_size;
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u32 txdl_per_memblock;
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u32 txdl_size;
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u32 txdl_priv_size;
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u32 per_txdl_space;
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u32 txdlblock_priv_size;
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u32 align_size;
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vxge_hal_fifo_callback_f callback;
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vxge_hal_fifo_txdl_init_f txdl_init;
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vxge_hal_fifo_txdl_term_f txdl_term;
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vxge_hal_vpath_stats_sw_fifo_info_t *stats;
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} __vxge_os_attr_cacheline_aligned __hal_fifo_t;
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/*
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* struct __hal_fifo_txdl_priv_t - Transmit descriptor HAL-private data.
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* @dma_addr: DMA (mapped) address of _this_ descriptor.
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* @dma_handle: DMA handle used to map the descriptor onto device.
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* @dma_offset: Descriptor's offset in the memory block. HAL allocates
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* descriptors in memory blocks (see vxge_hal_fifo_config_t {})
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* Each memblock is a contiguous block of DMA-able memory.
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* @frags: Total number of fragments (that is, contiguous data buffers)
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* carried by this TxDL.
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* @align_vaddr_start: Aligned virtual address start
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* @align_vaddr: Virtual address of the per-TxDL area in memory used for
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* alignement. Used to place one or more mis-aligned fragments
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* (the maximum defined by configration variable
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* @max_aligned_frags).
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* @align_dma_addr: DMA address translated from the @align_vaddr.
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* @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
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* @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
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* @align_dma_offset: The current offset into the @align_vaddr area.
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* Grows while filling the descriptor, gets reset.
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* @align_used_frags: Number of fragments used.
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* @alloc_frags: Total number of fragments allocated.
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* @dang_frags: Number of fragments kept from release until this TxDL is freed.
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* @bytes_sent:
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* @unused:
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* @dang_txdl:
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* @next_txdl_priv:
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* @first_txdp:
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* @dang_txdlh: Pointer to TxDL (list) kept from release until this TxDL
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* is freed.
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* @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
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* TxDL list.
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* @txdlh: Corresponding txdlh to this TxDL.
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* @memblock: Pointer to the TxDL memory block or memory page.
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* on the next send operation.
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* @dma_object: DMA address and handle of the memory block that contains
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* the descriptor. This member is used only in the "checked"
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* version of the HAL (to enforce certain assertions);
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* otherwise it gets compiled out.
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* @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
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*
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* Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA
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* information associated with the descriptor. Note that ULD can ask HAL
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* to allocate additional per-descriptor space for its own (ULD-specific)
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* purposes.
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*
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* See also: vxge_hal_ring_rxd_priv_t {}.
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*/
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typedef struct __hal_fifo_txdl_priv_t {
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dma_addr_t dma_addr;
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pci_dma_h dma_handle;
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ptrdiff_t dma_offset;
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u32 frags;
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u8 *align_vaddr_start;
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u8 *align_vaddr;
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dma_addr_t align_dma_addr;
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pci_dma_h align_dma_handle;
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pci_dma_acc_h align_dma_acch;
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ptrdiff_t align_dma_offset;
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u32 align_used_frags;
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u32 alloc_frags;
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u32 dang_frags;
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u32 bytes_sent;
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u32 unused;
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vxge_hal_fifo_txd_t *dang_txdl;
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struct __hal_fifo_txdl_priv_t *next_txdl_priv;
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vxge_hal_fifo_txd_t *first_txdp;
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void *memblock;
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#if defined(VXGE_DEBUG_ASSERT)
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vxge_hal_mempool_dma_t *dma_object;
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#endif
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#if defined(VXGE_OS_MEMORY_CHECK)
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u32 allocated;
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#endif
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} __hal_fifo_txdl_priv_t;
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#define VXGE_HAL_FIFO_ULD_PRIV(fifo, txdh) \
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fifo->channel.dtr_arr[ \
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((vxge_hal_fifo_txd_t *)(txdh))->host_control].uld_priv
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#define VXGE_HAL_FIFO_HAL_PRIV(fifo, txdh) \
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((__hal_fifo_txdl_priv_t *)(fifo->channel.dtr_arr[ \
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((vxge_hal_fifo_txd_t *)(txdh))->host_control].hal_priv))
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#define VXGE_HAL_FIFO_MAX_FRAG_CNT(fifo) fifo->config->max_frags
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#define VXGE_HAL_FIFO_TXDL_INDEX(txdp) \
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(u32)((vxge_hal_fifo_txd_t *)txdp)->host_control
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/* ========================= FIFO PRIVATE API ============================= */
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vxge_hal_status_e
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__hal_fifo_create(
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vxge_hal_vpath_h vpath_handle,
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vxge_hal_fifo_attr_t *attr);
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void
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__hal_fifo_abort(
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vxge_hal_fifo_h fifoh,
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vxge_hal_reopen_e reopen);
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vxge_hal_status_e
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__hal_fifo_reset(
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vxge_hal_fifo_h ringh);
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void
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__hal_fifo_delete(
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vxge_hal_vpath_h vpath_handle);
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void
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__hal_fifo_txdl_free_many(
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__hal_fifo_t *fifo,
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vxge_hal_fifo_txd_t *txdp,
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u32 list_size,
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u32 frags);
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#if defined(VXGE_HAL_ALIGN_XMIT)
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void
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__hal_fifo_txdl_align_free_unmap(
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__hal_fifo_t *fifo,
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vxge_hal_fifo_txd_t *txdp);
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vxge_hal_status_e
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__hal_fifo_txdl_align_alloc_map(
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__hal_fifo_t *fifo,
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vxge_hal_fifo_txd_t *txdp);
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#endif
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__EXTERN_END_DECLS
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#endif /* VXGE_HAL_FIFO_H */
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