freebsd-skq/sys/boot/fdt/dts/arm/h3.dtsi

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/*-
* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
cpus {
cpu0: cpu@0 {
clocks = <&ccu CLK_CPUX>;
clock-latency = <2000000>;
};
};
soc {
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
reg-names = "emac", "syscon";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
reset-names = "ahb", "ephy";
clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
clock-names = "ahb", "ephy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
r_i2c: i2c@1f02400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01f02400 0x400>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
sid: eeprom@1c14000 {
compatible = "allwinner,sun8i-a83t-sid";
reg = <0x01c14000 0x400>;
};
rtp: rtp@1c25000 {
compatible = "allwinner,sun8i-h3-ts";
reg = <0x01c25000 0x400>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
clock-names = "ahb", "ths";
resets = <&ccu RST_BUS_THS 8>;
#thermal-sensor-cells = <0>;
};
/* codec: codec@01c22c00 { */
/* compatible = "allwinner,sun8i-h3-codec"; */
/* reg = <0x01c22c00 0x100>, <0x01f015c0 0x4>; */
/* reg-names = "codec", "pr"; */
/* interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; */
/* clocks = <&ccu CLK_BUS_CODEC>, <&codec_clk>; */
/* clock-names = "ahb", "codec"; */
/* resets = <&ahb_rst 128>; */
/* reset-names = "ahb"; */
/* dmas = <&dma 15>, <&dma 15>; */
/* dma-names = "rx", "tx"; */
/* status = "disabled"; */
/* }; */
};
};
&pio {
emac_pins_rgmii_a: emac_rgmii@0 {
allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
"PD7", "PD8", "PD9", "PD10", "PD12", "PD13",
"PD15", "PD16", "PD17";
allwinner,function = "emac";
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
emac_phy_reset_pin: emac_phy_reset_pin@0 {
allwinner,pins = "PD6";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};