110 lines
3.5 KiB
Plaintext
110 lines
3.5 KiB
Plaintext
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/ {
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cpus {
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cpu0: cpu@0 {
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clocks = <&ccu CLK_CPUX>;
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clock-latency = <2000000>;
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};
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};
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soc {
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emac: ethernet@1c30000 {
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compatible = "allwinner,sun8i-h3-emac";
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reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
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reg-names = "emac", "syscon";
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
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reset-names = "ahb", "ephy";
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clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
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clock-names = "ahb", "ephy";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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r_i2c: i2c@1f02400 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01f02400 0x400>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sid: eeprom@1c14000 {
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compatible = "allwinner,sun8i-a83t-sid";
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reg = <0x01c14000 0x400>;
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};
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rtp: rtp@1c25000 {
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compatible = "allwinner,sun8i-h3-ts";
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reg = <0x01c25000 0x400>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
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clock-names = "ahb", "ths";
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resets = <&ccu RST_BUS_THS 8>;
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#thermal-sensor-cells = <0>;
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};
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/* codec: codec@01c22c00 { */
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/* compatible = "allwinner,sun8i-h3-codec"; */
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/* reg = <0x01c22c00 0x100>, <0x01f015c0 0x4>; */
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/* reg-names = "codec", "pr"; */
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/* interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; */
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/* clocks = <&ccu CLK_BUS_CODEC>, <&codec_clk>; */
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/* clock-names = "ahb", "codec"; */
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/* resets = <&ahb_rst 128>; */
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/* reset-names = "ahb"; */
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/* dmas = <&dma 15>, <&dma 15>; */
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/* dma-names = "rx", "tx"; */
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/* status = "disabled"; */
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/* }; */
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};
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};
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&pio {
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emac_pins_rgmii_a: emac_rgmii@0 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
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"PD7", "PD8", "PD9", "PD10", "PD12", "PD13",
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"PD15", "PD16", "PD17";
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allwinner,function = "emac";
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allwinner,drive = <SUN4I_PINCTRL_40_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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emac_phy_reset_pin: emac_phy_reset_pin@0 {
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allwinner,pins = "PD6";
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allwinner,function = "gpio_out";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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};
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