436ddce665
cortex-a5 cores unlike the aml8726-m8 which has cortex-a9 cores). Submitted by: John Wehle Reviewed by: imp
80 lines
2.1 KiB
Plaintext
80 lines
2.1 KiB
Plaintext
/*-
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* Copyright (c) 2015 John Wehle <john@feith.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/include/ "meson.dtsi"
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/ {
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model = "Amlogic Meson8b SoC";
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compatible = "amlogic,meson8b";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x200>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x201>;
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};
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cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x202>;
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};
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cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x203>;
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};
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};
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clk81: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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&L2 {
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interrupts = <0 143 1>;
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};
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