9346e9130d
needed in later changes where we may not be able to lock the pic list lock to perform a lookup, e.g. from within interrupt context. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
905 lines
22 KiB
C
905 lines
22 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Tegra GPIO driver.
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*/
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/gpio.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "pic_if.h"
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#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \
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device_get_nameunit(_sc->dev), "tegra_gpio", MTX_DEF)
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#define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
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#define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
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#define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED);
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#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
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#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
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#define GPIO_BANK_OFFS 0x100 /* Bank offset */
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#define GPIO_NUM_BANKS 8 /* Total number per bank */
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#define GPIO_REGS_IN_BANK 4 /* Total registers in bank */
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#define GPIO_PINS_IN_REG 8 /* Total pin in register */
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#define GPIO_BANKNUM(n) ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG))
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#define GPIO_PORTNUM(n) (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK)
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#define GPIO_BIT(n) ((n) % GPIO_PINS_IN_REG)
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#define GPIO_REGNUM(n) (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \
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GPIO_PORTNUM(n) * 4)
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#define NGPIO ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8)
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/* Register offsets */
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#define GPIO_CNF 0x00
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#define GPIO_OE 0x10
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#define GPIO_OUT 0x20
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#define GPIO_IN 0x30
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#define GPIO_INT_STA 0x40
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#define GPIO_INT_ENB 0x50
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#define GPIO_INT_LVL 0x60
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#define GPIO_INT_LVL_DELTA (1 << 16)
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#define GPIO_INT_LVL_EDGE (1 << 8)
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#define GPIO_INT_LVL_HIGH (1 << 0)
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#define GPIO_INT_LVL_MASK (GPIO_INT_LVL_DELTA | \
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GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH)
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#define GPIO_INT_CLR 0x70
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#define GPIO_MSK_CNF 0x80
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#define GPIO_MSK_OE 0x90
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#define GPIO_MSK_OUT 0xA0
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#define GPIO_MSK_INT_STA 0xC0
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#define GPIO_MSK_INT_ENB 0xD0
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#define GPIO_MSK_INT_LVL 0xE0
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char *tegra_gpio_port_names[] = {
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"A", "B", "C", "D", /* Bank 0 */
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"E", "F", "G", "H", /* Bank 1 */
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"I", "J", "K", "L", /* Bank 2 */
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"M", "N", "O", "P", /* Bank 3 */
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"Q", "R", "S", "T", /* Bank 4 */
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"U", "V", "W", "X", /* Bank 5 */
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"Y", "Z", "AA", "BB", /* Bank 6 */
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"CC", "DD", "EE" /* Bank 7 */
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};
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struct tegra_gpio_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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uint32_t cfgreg;
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};
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struct tegra_gpio_softc;
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struct tegra_gpio_irq_cookie {
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struct tegra_gpio_softc *sc;
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int bank_num;
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};
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struct tegra_gpio_softc {
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device_t dev;
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device_t busdev;
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struct mtx mtx;
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struct resource *mem_res;
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struct resource *irq_res[GPIO_NUM_BANKS];
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void *irq_ih[GPIO_NUM_BANKS];
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struct tegra_gpio_irq_cookie irq_cookies[GPIO_NUM_BANKS];
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int gpio_npins;
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struct gpio_pin gpio_pins[NGPIO];
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struct tegra_gpio_irqsrc *isrcs;
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};
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-gpio", 1},
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{NULL, 0}
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};
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/* --------------------------------------------------------------------------
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*
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* GPIO
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*
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*/
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static inline void
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gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg,
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struct gpio_pin *pin, uint32_t val)
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{
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uint32_t tmp;
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int bit;
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bit = GPIO_BIT(pin->gp_pin);
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tmp = 0x100 << bit; /* mask */
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tmp |= (val & 1) << bit; /* value */
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bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp);
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}
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static inline uint32_t
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gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin)
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{
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int bit;
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uint32_t val;
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bit = GPIO_BIT(pin->gp_pin);
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val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin));
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return (val >> bit) & 1;
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}
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static void
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tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin,
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unsigned int flags)
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{
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if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0)
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return;
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/* Manage input/output */
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pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
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if (flags & GPIO_PIN_OUTPUT) {
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pin->gp_flags |= GPIO_PIN_OUTPUT;
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gpio_write_masked(sc, GPIO_MSK_OE, pin, 1);
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} else {
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pin->gp_flags |= GPIO_PIN_INPUT;
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gpio_write_masked(sc, GPIO_MSK_OE, pin, 0);
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}
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}
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static device_t
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tegra_gpio_get_bus(device_t dev)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->busdev);
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}
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static int
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tegra_gpio_pin_max(device_t dev, int *maxpin)
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{
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*maxpin = NGPIO - 1;
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return (0);
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}
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static int
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tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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*caps = sc->gpio_pins[pin].gp_caps;
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct tegra_gpio_softc *sc;
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int cnf;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]);
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if (cnf == 0) {
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GPIO_UNLOCK(sc);
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return (ENXIO);
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}
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*flags = sc->gpio_pins[pin].gp_flags;
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct tegra_gpio_softc *sc;
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int cnf;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]);
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if (cnf == 0) {
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/* XXX - allow this for while ....
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GPIO_UNLOCK(sc);
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return (ENXIO);
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*/
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gpio_write_masked(sc, GPIO_MSK_CNF, &sc->gpio_pins[pin], 1);
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}
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tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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*val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin],
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gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1);
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GPIO_UNLOCK(sc);
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return (0);
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}
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/* --------------------------------------------------------------------------
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*
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* Interrupts
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*
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*/
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static inline void
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intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg,
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struct tegra_gpio_irqsrc *tgi, uint32_t val)
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{
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uint32_t tmp;
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int bit;
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bit = GPIO_BIT(tgi->irq);
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tmp = 0x100 << bit; /* mask */
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tmp |= (val & 1) << bit; /* value */
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bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);
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}
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static inline void
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intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg,
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struct tegra_gpio_irqsrc *tgi, uint32_t val, uint32_t mask)
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{
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uint32_t tmp;
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int bit;
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bit = GPIO_BIT(tgi->irq);
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GPIO_LOCK(sc);
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tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq));
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tmp &= ~(mask << bit);
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tmp |= val << bit;
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bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);
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GPIO_UNLOCK(sc);
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}
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static inline void
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tegra_gpio_isrc_mask(struct tegra_gpio_softc *sc,
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struct tegra_gpio_irqsrc *tgi, uint32_t val)
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{
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intr_write_masked(sc, GPIO_MSK_INT_ENB, tgi, val);
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}
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static inline void
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tegra_gpio_isrc_eoi(struct tegra_gpio_softc *sc,
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struct tegra_gpio_irqsrc *tgi)
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{
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intr_write_masked(sc, GPIO_INT_CLR, tgi, 1);
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}
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static inline bool
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tegra_gpio_isrc_is_level(struct tegra_gpio_irqsrc *tgi)
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{
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return (tgi->cfgreg & GPIO_INT_LVL_EDGE);
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}
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static int
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tegra_gpio_intr(void *arg)
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{
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u_int irq, i, j, val, basepin;
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struct tegra_gpio_softc *sc;
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struct trapframe *tf;
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struct tegra_gpio_irqsrc *tgi;
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struct tegra_gpio_irq_cookie *cookie;
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cookie = (struct tegra_gpio_irq_cookie *)arg;
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sc = cookie->sc;
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tf = curthread->td_intr_frame;
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for (i = 0; i < GPIO_REGS_IN_BANK; i++) {
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basepin = cookie->bank_num * GPIO_REGS_IN_BANK *
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GPIO_PINS_IN_REG + i * GPIO_PINS_IN_REG;
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val = bus_read_4(sc->mem_res, GPIO_INT_STA +
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GPIO_REGNUM(basepin));
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val &= bus_read_4(sc->mem_res, GPIO_INT_ENB +
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GPIO_REGNUM(basepin));
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/* Interrupt handling */
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for (j = 0; j < GPIO_PINS_IN_REG; j++) {
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if ((val & (1 << j)) == 0)
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continue;
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irq = basepin + j;
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tgi = &sc->isrcs[irq];
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if (!tegra_gpio_isrc_is_level(tgi))
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tegra_gpio_isrc_eoi(sc, tgi);
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if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
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tegra_gpio_isrc_mask(sc, tgi, 0);
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if (tegra_gpio_isrc_is_level(tgi))
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tegra_gpio_isrc_eoi(sc, tgi);
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device_printf(sc->dev,
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"Stray irq %u disabled\n", irq);
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}
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}
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}
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return (FILTER_HANDLED);
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}
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|
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static int
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tegra_gpio_pic_attach(struct tegra_gpio_softc *sc)
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{
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int error;
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uint32_t irq;
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const char *name;
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sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF,
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M_WAITOK | M_ZERO);
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name = device_get_nameunit(sc->dev);
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for (irq = 0; irq < sc->gpio_npins; irq++) {
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sc->isrcs[irq].irq = irq;
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sc->isrcs[irq].cfgreg = 0;
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error = intr_isrc_register(&sc->isrcs[irq].isrc,
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sc->dev, 0, "%s,%u", name, irq);
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if (error != 0)
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return (error); /* XXX deregister ISRCs */
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}
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|
if (intr_pic_register(sc->dev,
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OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL)
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return (ENXIO);
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return (0);
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}
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|
|
static int
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tegra_gpio_pic_detach(struct tegra_gpio_softc *sc)
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{
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|
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/*
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* There has not been established any procedure yet
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* how to detach PIC from living system correctly.
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|
*/
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device_printf(sc->dev, "%s: not implemented yet\n", __func__);
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return (EBUSY);
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}
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|
|
|
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static void
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tegra_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
|
|
{
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struct tegra_gpio_softc *sc;
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struct tegra_gpio_irqsrc *tgi;
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sc = device_get_softc(dev);
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tgi = (struct tegra_gpio_irqsrc *)isrc;
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tegra_gpio_isrc_mask(sc, tgi, 0);
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}
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|
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static void
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tegra_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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|
{
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|
struct tegra_gpio_softc *sc;
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|
struct tegra_gpio_irqsrc *tgi;
|
|
|
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sc = device_get_softc(dev);
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|
tgi = (struct tegra_gpio_irqsrc *)isrc;
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tegra_gpio_isrc_mask(sc, tgi, 1);
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}
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|
|
static int
|
|
tegra_gpio_pic_map_fdt(struct tegra_gpio_softc *sc, u_int ncells,
|
|
pcell_t *cells, u_int *irqp, uint32_t *regp)
|
|
{
|
|
uint32_t reg;
|
|
|
|
/*
|
|
* The first cell is the interrupt number.
|
|
* The second cell is used to specify flags:
|
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* bits[3:0] trigger type and level flags:
|
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* 1 = low-to-high edge triggered.
|
|
* 2 = high-to-low edge triggered.
|
|
* 4 = active high level-sensitive.
|
|
* 8 = active low level-sensitive.
|
|
*/
|
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if (ncells != 2 || cells[0] >= sc->gpio_npins)
|
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return (EINVAL);
|
|
|
|
/*
|
|
* All interrupt types could be set for an interrupt at one moment.
|
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* At least, the combination of 'low-to-high' and 'high-to-low' edge
|
|
* triggered interrupt types can make a sense.
|
|
*/
|
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if (cells[1] == 1)
|
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reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH;
|
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else if (cells[1] == 2)
|
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reg = GPIO_INT_LVL_EDGE;
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else if (cells[1] == 3)
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reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA;
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else if (cells[1] == 4)
|
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reg = GPIO_INT_LVL_HIGH;
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else if (cells[1] == 8)
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reg = 0;
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else
|
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return (EINVAL);
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|
|
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*irqp = cells[0];
|
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if (regp != NULL)
|
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*regp = reg;
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return (0);
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}
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|
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|
|
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static int
|
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tegra_gpio_pic_map_gpio(struct tegra_gpio_softc *sc, u_int gpio_pin_num,
|
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u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, uint32_t *regp)
|
|
{
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|
|
|
uint32_t reg;
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|
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if (gpio_pin_num >= sc->gpio_npins)
|
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return (EINVAL);
|
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switch (intr_mode) {
|
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case GPIO_INTR_CONFORM:
|
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case GPIO_INTR_LEVEL_LOW:
|
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reg = 0;
|
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break;
|
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case GPIO_INTR_LEVEL_HIGH:
|
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reg = GPIO_INT_LVL_HIGH;
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break;
|
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case GPIO_INTR_EDGE_RISING:
|
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reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH;
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break;
|
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case GPIO_INTR_EDGE_FALLING:
|
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reg = GPIO_INT_LVL_EDGE;
|
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break;
|
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case GPIO_INTR_EDGE_BOTH:
|
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reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA;
|
|
break;
|
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default:
|
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return (EINVAL);
|
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}
|
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*irqp = gpio_pin_num;
|
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if (regp != NULL)
|
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*regp = reg;
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return (0);
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}
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|
|
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static int
|
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tegra_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
|
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struct intr_irqsrc **isrcp)
|
|
{
|
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int rv;
|
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u_int irq;
|
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struct tegra_gpio_softc *sc;
|
|
|
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sc = device_get_softc(dev);
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|
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if (data->type == INTR_MAP_DATA_FDT) {
|
|
struct intr_map_data_fdt *daf;
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|
|
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daf = (struct intr_map_data_fdt *)data;
|
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rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq,
|
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NULL);
|
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} else if (data->type == INTR_MAP_DATA_GPIO) {
|
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struct intr_map_data_gpio *dag;
|
|
|
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dag = (struct intr_map_data_gpio *)data;
|
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rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num,
|
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dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL);
|
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} else
|
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return (ENOTSUP);
|
|
|
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if (rv == 0)
|
|
*isrcp = &sc->isrcs[irq].isrc;
|
|
return (rv);
|
|
}
|
|
|
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static void
|
|
tegra_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct tegra_gpio_softc *sc;
|
|
struct tegra_gpio_irqsrc *tgi;
|
|
|
|
sc = device_get_softc(dev);
|
|
tgi = (struct tegra_gpio_irqsrc *)isrc;
|
|
if (tegra_gpio_isrc_is_level(tgi))
|
|
tegra_gpio_isrc_eoi(sc, tgi);
|
|
}
|
|
|
|
static void
|
|
tegra_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct tegra_gpio_softc *sc;
|
|
struct tegra_gpio_irqsrc *tgi;
|
|
|
|
sc = device_get_softc(dev);
|
|
tgi = (struct tegra_gpio_irqsrc *)isrc;
|
|
tegra_gpio_isrc_mask(sc, tgi, 1);
|
|
}
|
|
|
|
static void
|
|
tegra_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct tegra_gpio_softc *sc;
|
|
struct tegra_gpio_irqsrc *tgi;
|
|
|
|
sc = device_get_softc(dev);
|
|
tgi = (struct tegra_gpio_irqsrc *)isrc;
|
|
|
|
tegra_gpio_isrc_mask(sc, tgi, 0);
|
|
if (tegra_gpio_isrc_is_level(tgi))
|
|
tegra_gpio_isrc_eoi(sc, tgi);
|
|
}
|
|
|
|
static int
|
|
tegra_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
u_int irq;
|
|
uint32_t cfgreg;
|
|
int rv;
|
|
struct tegra_gpio_softc *sc;
|
|
struct tegra_gpio_irqsrc *tgi;
|
|
|
|
sc = device_get_softc(dev);
|
|
tgi = (struct tegra_gpio_irqsrc *)isrc;
|
|
|
|
if (data == NULL)
|
|
return (ENOTSUP);
|
|
|
|
/* Get and check config for an interrupt. */
|
|
if (data->type == INTR_MAP_DATA_FDT) {
|
|
struct intr_map_data_fdt *daf;
|
|
|
|
daf = (struct intr_map_data_fdt *)data;
|
|
rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq,
|
|
&cfgreg);
|
|
} else if (data->type == INTR_MAP_DATA_GPIO) {
|
|
struct intr_map_data_gpio *dag;
|
|
|
|
dag = (struct intr_map_data_gpio *)data;
|
|
rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num,
|
|
dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, &cfgreg);
|
|
} else
|
|
return (ENOTSUP);
|
|
if (rv != 0)
|
|
return (EINVAL);
|
|
|
|
/*
|
|
* If this is a setup for another handler,
|
|
* only check that its configuration match.
|
|
*/
|
|
if (isrc->isrc_handlers != 0)
|
|
return (tgi->cfgreg == cfgreg ? 0 : EINVAL);
|
|
|
|
tgi->cfgreg = cfgreg;
|
|
intr_write_modify(sc, GPIO_INT_LVL, tgi, cfgreg, GPIO_INT_LVL_MASK);
|
|
tegra_gpio_pic_enable_intr(dev, isrc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
struct tegra_gpio_softc *sc;
|
|
struct tegra_gpio_irqsrc *tgi;
|
|
|
|
sc = device_get_softc(dev);
|
|
tgi = (struct tegra_gpio_irqsrc *)isrc;
|
|
|
|
if (isrc->isrc_handlers == 0)
|
|
tegra_gpio_isrc_mask(sc, tgi, 0);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra_gpio_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
|
|
device_set_desc(dev, "Tegra GPIO Controller");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* --------------------------------------------------------------------------
|
|
*
|
|
* Bus
|
|
*
|
|
*/
|
|
static int
|
|
tegra_gpio_detach(device_t dev)
|
|
{
|
|
struct tegra_gpio_softc *sc;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized"));
|
|
|
|
for (i = 0; i < GPIO_NUM_BANKS; i++) {
|
|
if (sc->irq_ih[i] != NULL)
|
|
bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]);
|
|
}
|
|
|
|
if (sc->isrcs != NULL)
|
|
tegra_gpio_pic_detach(sc);
|
|
|
|
gpiobus_detach_bus(dev);
|
|
|
|
for (i = 0; i < GPIO_NUM_BANKS; i++) {
|
|
if (sc->irq_res[i] != NULL)
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0,
|
|
sc->irq_res[i]);
|
|
}
|
|
if (sc->mem_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
|
|
GPIO_LOCK_DESTROY(sc);
|
|
|
|
return(0);
|
|
}
|
|
|
|
static int
|
|
tegra_gpio_attach(device_t dev)
|
|
{
|
|
struct tegra_gpio_softc *sc;
|
|
int i, rid;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
GPIO_LOCK_INIT(sc);
|
|
|
|
/* Allocate bus_space resources. */
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->mem_res == NULL) {
|
|
device_printf(dev, "Cannot allocate memory resources\n");
|
|
tegra_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->gpio_npins = NGPIO;
|
|
for (i = 0; i < sc->gpio_npins; i++) {
|
|
sc->gpio_pins[i].gp_pin = i;
|
|
sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
|
|
GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH |
|
|
GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING |
|
|
GPIO_INTR_EDGE_BOTH;
|
|
snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d",
|
|
tegra_gpio_port_names[ i / GPIO_PINS_IN_REG],
|
|
i % GPIO_PINS_IN_REG);
|
|
sc->gpio_pins[i].gp_flags =
|
|
gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ?
|
|
GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
|
|
}
|
|
|
|
/* Init interrupt related registes. */
|
|
for (i = 0; i < sc->gpio_npins; i += GPIO_PINS_IN_REG) {
|
|
bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0);
|
|
bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF);
|
|
bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF);
|
|
}
|
|
|
|
/* Allocate interrupts. */
|
|
for (i = 0; i < GPIO_NUM_BANKS; i++) {
|
|
sc->irq_cookies[i].sc = sc;
|
|
sc->irq_cookies[i].bank_num = i;
|
|
rid = i;
|
|
sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
|
|
&rid, RF_ACTIVE);
|
|
if (sc->irq_res[i] == NULL) {
|
|
device_printf(dev, "Cannot allocate IRQ resources\n");
|
|
tegra_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
if ((bus_setup_intr(dev, sc->irq_res[i],
|
|
INTR_TYPE_MISC | INTR_MPSAFE, tegra_gpio_intr, NULL,
|
|
&sc->irq_cookies[i], &sc->irq_ih[i]))) {
|
|
device_printf(dev,
|
|
"WARNING: unable to register interrupt handler\n");
|
|
tegra_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
|
|
if (tegra_gpio_pic_attach(sc) != 0) {
|
|
device_printf(dev, "WARNING: unable to attach PIC\n");
|
|
tegra_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->busdev = gpiobus_attach_bus(dev);
|
|
if (sc->busdev == NULL) {
|
|
tegra_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (bus_generic_attach(dev));
|
|
}
|
|
|
|
static int
|
|
tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent,
|
|
int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags)
|
|
{
|
|
|
|
if (gcells != 2)
|
|
return (ERANGE);
|
|
*pin = gpios[0];
|
|
*flags= gpios[1];
|
|
return (0);
|
|
}
|
|
|
|
static phandle_t
|
|
tegra_gpio_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
/* We only have one child, the GPIO bus, which needs our own node. */
|
|
return (ofw_bus_get_node(bus));
|
|
}
|
|
|
|
static device_method_t tegra_gpio_methods[] = {
|
|
DEVMETHOD(device_probe, tegra_gpio_probe),
|
|
DEVMETHOD(device_attach, tegra_gpio_attach),
|
|
DEVMETHOD(device_detach, tegra_gpio_detach),
|
|
|
|
/* Interrupt controller interface */
|
|
DEVMETHOD(pic_disable_intr, tegra_gpio_pic_disable_intr),
|
|
DEVMETHOD(pic_enable_intr, tegra_gpio_pic_enable_intr),
|
|
DEVMETHOD(pic_map_intr, tegra_gpio_pic_map_intr),
|
|
DEVMETHOD(pic_setup_intr, tegra_gpio_pic_setup_intr),
|
|
DEVMETHOD(pic_teardown_intr, tegra_gpio_pic_teardown_intr),
|
|
DEVMETHOD(pic_post_filter, tegra_gpio_pic_post_filter),
|
|
DEVMETHOD(pic_post_ithread, tegra_gpio_pic_post_ithread),
|
|
DEVMETHOD(pic_pre_ithread, tegra_gpio_pic_pre_ithread),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_get_bus, tegra_gpio_get_bus),
|
|
DEVMETHOD(gpio_pin_max, tegra_gpio_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, tegra_gpio_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, tegra_gpio_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, tegra_gpio_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, tegra_gpio_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, tegra_gpio_pin_get),
|
|
DEVMETHOD(gpio_pin_set, tegra_gpio_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, tegra_gpio_pin_toggle),
|
|
DEVMETHOD(gpio_map_gpios, tegra_map_gpios),
|
|
|
|
/* ofw_bus interface */
|
|
DEVMETHOD(ofw_bus_get_node, tegra_gpio_get_node),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t tegra_gpio_driver = {
|
|
"tegra_gpio",
|
|
tegra_gpio_methods,
|
|
sizeof(struct tegra_gpio_softc),
|
|
};
|
|
static devclass_t tegra_gpio_devclass;
|
|
|
|
EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver,
|
|
tegra_gpio_devclass, 0, 0, 70);
|
|
|
|
extern devclass_t ofwgpiobus_devclass;
|
|
extern driver_t ofw_gpiobus_driver;
|
|
EARLY_DRIVER_MODULE(ofw_gpiobus, tegra_gpio, ofw_gpiobus_driver,
|
|
ofwgpiobus_devclass, 0, 0, BUS_PASS_BUS);
|
|
extern devclass_t gpioc_devclass;
|
|
extern driver_t gpioc_driver;
|
|
DRIVER_MODULE(gpioc, tegra_gpio, gpioc_driver, gpioc_devclass, 0, 0);
|