370 lines
13 KiB
C
370 lines
13 KiB
C
/* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */
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/*-
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* Copyright (c) 1994 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the RiscBSD team.
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* 4. The name "RiscBSD" nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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#define PDSHIFT 20 /* LOG2(NBPDR) */
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#define NBPD (1 << PDSHIFT) /* bytes/page dir */
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#define NPTEPD (NBPD / PAGE_SIZE)
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#ifndef LOCORE
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typedef uint32_t pd_entry_t; /* page directory entry */
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typedef uint32_t pt_entry_t; /* page table entry */
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#endif
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#define PD_MASK 0xfff00000 /* page directory address bits */
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#define PT_MASK 0x000ff000 /* page table address bits */
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#define PG_FRAME 0xfffff000
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/* The PT_SIZE definition is misleading... A page table is only 0x400
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* bytes long. But since VM mapping can only be done to 0x1000 a single
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* 1KB blocks cannot be steered to a va by itself. Therefore the
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* pages tables are allocated in blocks of 4. i.e. if a 1 KB block
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* was allocated for a PT then the other 3KB would also get mapped
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* whenever the 1KB was mapped.
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*/
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#define PT_RSIZE 0x0400 /* Real page table size */
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#define PT_SIZE 0x1000
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#define PD_SIZE 0x4000
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/* Page table types and masks */
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#define L1_PAGE 0x01 /* L1 page table mapping */
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#define L1_SECTION 0x02 /* L1 section mapping */
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#define L1_FPAGE 0x03 /* L1 fine page mapping */
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#define L1_MASK 0x03 /* Mask for L1 entry type */
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#define L2_LPAGE 0x01 /* L2 large page (64KB) */
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#define L2_SPAGE 0x02 /* L2 small page (4KB) */
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#define L2_MASK 0x03 /* Mask for L2 entry type */
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#define L2_INVAL 0x00 /* L2 invalid type */
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/* PTE construction macros */
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#define L2_LPTE(p, a, f) ((p) | PT_AP(a) | L2_LPAGE | (f))
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#define L2_SPTE(p, a, f) ((p) | PT_AP(a) | L2_SPAGE | (f))
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#define L2_PTE(p, a) L2_SPTE((p), (a), PT_CACHEABLE)
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#define L2_PTE_NC(p, a) L2_SPTE((p), (a), PT_B)
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#define L2_PTE_NC_NB(p, a) L2_SPTE((p), (a), 0)
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#define L1_SECPTE(p, a, f) ((p) | ((a) << AP_SECTION_SHIFT) | (f) \
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| L1_SECTION | PT_U)
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#define L1_PTE(p) ((p) | 0x00 | L1_PAGE | PT_U)
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#define L1_SEC(p, c) L1_SECPTE((p), AP_KRW, (c))
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#define L1_SEC_SIZE (1 << PDSHIFT)
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#define L2_LPAGE_SIZE (NBPG * 16)
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/* Domain types */
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#define DOMAIN_FAULT 0x00
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#define DOMAIN_CLIENT 0x01
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#define DOMAIN_RESERVED 0x02
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#define DOMAIN_MANAGER 0x03
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/* L1 and L2 address masks */
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#define L1_ADDR_MASK 0xfffffc00
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#define L2_ADDR_MASK 0xfffff000
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/*
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* The ARM MMU architecture was introduced with ARM v3 (previous ARM
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* architecture versions used an optional off-CPU memory controller
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* to perform address translation).
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*
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* The ARM MMU consists of a TLB and translation table walking logic.
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* There is typically one TLB per memory interface (or, put another
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* way, one TLB per software-visible cache).
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*
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* The ARM MMU is capable of mapping memory in the following chunks:
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*
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* 1M Sections (L1 table)
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*
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* 64K Large Pages (L2 table)
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*
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* 4K Small Pages (L2 table)
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*
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* 1K Tiny Pages (L2 table)
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*
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* There are two types of L2 tables: Coarse Tables and Fine Tables.
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* Coarse Tables can map Large and Small Pages. Fine Tables can
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* map Tiny Pages.
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*
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* Coarse Tables can define 4 Subpages within Large and Small pages.
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* Subpages define different permissions for each Subpage within
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* a Page.
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*
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* Coarse Tables are 1K in length. Fine tables are 4K in length.
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*
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* The Translation Table Base register holds the pointer to the
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* L1 Table. The L1 Table is a 16K contiguous chunk of memory
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* aligned to a 16K boundary. Each entry in the L1 Table maps
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* 1M of virtual address space, either via a Section mapping or
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* via an L2 Table.
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*
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* In addition, the Fast Context Switching Extension (FCSE) is available
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* on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating
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* TLB/cache flushes on context switch by use of a smaller address space
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* and a "process ID" that modifies the virtual address before being
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* presented to the translation logic.
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*/
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/* ARMv6 super-sections. */
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#define L1_SUP_SIZE 0x01000000 /* 16M */
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#define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
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#define L1_SUP_FRAME (~L1_SUP_OFFSET)
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#define L1_SUP_SHIFT 24
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#define L1_S_SIZE 0x00100000 /* 1M */
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#define L1_S_OFFSET (L1_S_SIZE - 1)
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#define L1_S_FRAME (~L1_S_OFFSET)
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#define L1_S_SHIFT 20
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#define L2_L_SIZE 0x00010000 /* 64K */
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#define L2_L_OFFSET (L2_L_SIZE - 1)
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#define L2_L_FRAME (~L2_L_OFFSET)
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#define L2_L_SHIFT 16
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#define L2_S_SIZE 0x00001000 /* 4K */
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#define L2_S_OFFSET (L2_S_SIZE - 1)
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#define L2_S_FRAME (~L2_S_OFFSET)
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#define L2_S_SHIFT 12
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#define L2_T_SIZE 0x00000400 /* 1K */
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#define L2_T_OFFSET (L2_T_SIZE - 1)
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#define L2_T_FRAME (~L2_T_OFFSET)
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#define L2_T_SHIFT 10
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/*
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* The NetBSD VM implementation only works on whole pages (4K),
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* whereas the ARM MMU's Coarse tables are sized in terms of 1K
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* (16K L1 table, 1K L2 table).
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*
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* So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
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* table.
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*/
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#define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */
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#define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
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#define L1_TABLE_SIZE 0x4000 /* 16K */
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#define L2_TABLE_SIZE 0x1000 /* 4K */
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/*
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* The new pmap deals with the 1KB coarse L2 tables by
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* allocating them from a pool. Until every port has been converted,
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* keep the old L2_TABLE_SIZE define lying around. Converted ports
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* should use L2_TABLE_SIZE_REAL until then.
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*/
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#define L2_TABLE_SIZE_REAL 0x400 /* 1K */
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/*
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* ARM L1 Descriptors
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*/
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#define L1_TYPE_INV 0x00 /* Invalid (fault) */
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#define L1_TYPE_C 0x01 /* Coarse L2 */
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#define L1_TYPE_S 0x02 /* Section */
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#define L1_TYPE_F 0x03 /* Fine L2 */
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#define L1_TYPE_MASK 0x03 /* mask of type bits */
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/* L1 Section Descriptor */
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#define L1_S_B 0x00000004 /* bufferable Section */
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#define L1_S_C 0x00000008 /* cacheable Section */
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#define L1_S_IMP 0x00000010 /* implementation defined */
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#define L1_S_DOM(x) ((x) << 5) /* domain */
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#define L1_S_DOM_MASK L1_S_DOM(0xf)
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#define L1_S_AP(x) ((x) << 10) /* access permissions */
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#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
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#define L1_SHARED (1 << 16)
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#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */
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#define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */
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#define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */
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/* L1 Coarse Descriptor */
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#define L1_C_IMP0 0x00000004 /* implementation defined */
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#define L1_C_IMP1 0x00000008 /* implementation defined */
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#define L1_C_IMP2 0x00000010 /* implementation defined */
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#define L1_C_DOM(x) ((x) << 5) /* domain */
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#define L1_C_DOM_MASK L1_C_DOM(0xf)
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#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
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#define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */
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/* L1 Fine Descriptor */
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#define L1_F_IMP0 0x00000004 /* implementation defined */
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#define L1_F_IMP1 0x00000008 /* implementation defined */
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#define L1_F_IMP2 0x00000010 /* implementation defined */
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#define L1_F_DOM(x) ((x) << 5) /* domain */
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#define L1_F_DOM_MASK L1_F_DOM(0xf)
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#define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */
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#define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */
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/*
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* ARM L2 Descriptors
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*/
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#define L2_TYPE_INV 0x00 /* Invalid (fault) */
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#define L2_TYPE_L 0x01 /* Large Page */
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#define L2_TYPE_S 0x02 /* Small Page */
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#define L2_TYPE_T 0x03 /* Tiny Page */
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#define L2_TYPE_MASK 0x03 /* mask of type bits */
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/*
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* This L2 Descriptor type is available on XScale processors
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* when using a Coarse L1 Descriptor. The Extended Small
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* Descriptor has the same format as the XScale Tiny Descriptor,
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* but describes a 4K page, rather than a 1K page.
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*/
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#define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */
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#define L2_B 0x00000004 /* Bufferable page */
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#define L2_C 0x00000008 /* Cacheable page */
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#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */
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#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */
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#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */
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#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */
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#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
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#define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */
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#define L2_XSCALE_L_S(x) (1 << 15) /* Shared */
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#define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */
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/*
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* Access Permissions for L1 and L2 Descriptors.
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*/
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#define AP_W 0x01 /* writable */
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#define AP_U 0x02 /* user */
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/*
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* Short-hand for common AP_* constants.
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*
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* Note: These values assume the S (System) bit is set and
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* the R (ROM) bit is clear in CP15 register 1.
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*/
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#define AP_KR 0x00 /* kernel read */
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#define AP_KRW 0x01 /* kernel read/write */
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#define AP_KRWUR 0x02 /* kernel read/write usr read */
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#define AP_KRWURW 0x03 /* kernel read/write usr read/write */
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/*
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* Domain Types for the Domain Access Control Register.
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*/
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#define DOMAIN_FAULT 0x00 /* no access */
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#define DOMAIN_CLIENT 0x01 /* client */
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#define DOMAIN_RESERVED 0x02 /* reserved */
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#define DOMAIN_MANAGER 0x03 /* manager */
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/*
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* Type Extension bits for XScale processors.
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*
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* Behavior of C and B when X == 0:
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*
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* C B Cacheable Bufferable Write Policy Line Allocate Policy
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* 0 0 N N - -
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* 0 1 N Y - -
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* 1 0 Y Y Write-through Read Allocate
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* 1 1 Y Y Write-back Read Allocate
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*
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* Behavior of C and B when X == 1:
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* C B Cacheable Bufferable Write Policy Line Allocate Policy
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* 0 0 - - - - DO NOT USE
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* 0 1 N Y - -
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* 1 0 Mini-Data - - -
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* 1 1 Y Y Write-back R/W Allocate
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*/
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#define TEX_XSCALE_X 0x01 /* X modifies C and B */
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#define TEX_XSCALE_E 0x02
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#define TEX_XSCALE_T 0x04
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/* Xscale core 3 */
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/*
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*
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* Cache attributes with L2 present, S = 0
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* T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
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* 0 0 0 0 0 N N - N N
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* 0 0 0 0 1 N N - N Y
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* 0 0 0 1 0 Y Y WT N Y
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* 0 0 0 1 1 Y Y WB Y Y
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* 0 0 1 0 0 N N - Y Y
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* 0 0 1 0 1 N N - N N
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* 0 0 1 1 0 Y Y - - N
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* 0 0 1 1 1 Y Y WT Y Y
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* 0 1 0 0 0 N N - N N
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* 0 1 0 0 1 N/A N/A N/A N/A N/A
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* 0 1 0 1 0 N/A N/A N/A N/A N/A
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* 0 1 0 1 1 N/A N/A N/A N/A N/A
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* 0 1 1 X X N/A N/A N/A N/A N/A
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* 1 X 0 0 0 N N - N Y
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* 1 X 0 0 1 Y N WB N Y
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* 1 X 0 1 0 Y N WT N Y
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* 1 X 0 1 1 Y N WB Y Y
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* 1 X 1 0 0 N N - Y Y
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* 1 X 1 0 1 Y Y WB Y Y
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* 1 X 1 1 0 Y Y WT Y Y
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* 1 X 1 1 1 Y Y WB Y Y
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*
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*
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*
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*
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* Cache attributes with L2 present, S = 1
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* T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
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* 0 0 0 0 0 N N - N N
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* 0 0 0 0 1 N N - N Y
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* 0 0 0 1 0 Y Y - N Y
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* 0 0 0 1 1 Y Y WT Y Y
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* 0 0 1 0 0 N N - Y Y
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* 0 0 1 0 1 N N - N N
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* 0 0 1 1 0 Y Y - - N
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* 0 0 1 1 1 Y Y WT Y Y
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* 0 1 0 0 0 N N - N N
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* 0 1 0 0 1 N/A N/A N/A N/A N/A
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* 0 1 0 1 0 N/A N/A N/A N/A N/A
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* 0 1 0 1 1 N/A N/A N/A N/A N/A
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* 0 1 1 X X N/A N/A N/A N/A N/A
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* 1 X 0 0 0 N N - N Y
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* 1 X 0 0 1 Y N - N Y
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* 1 X 0 1 0 Y N - N Y
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* 1 X 0 1 1 Y N - Y Y
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* 1 X 1 0 0 N N - Y Y
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* 1 X 1 0 1 Y Y WT Y Y
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* 1 X 1 1 0 Y Y WT Y Y
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* 1 X 1 1 1 Y Y WT Y Y
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*/
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#endif /* !_MACHINE_PTE_H_ */
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/* End of pte.h */
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