e113789bdc
work in FreeBSD. This is still heavily a work in progress but I'd rather it start shipping in -HEAD sooner rather than later. This doesn't (yet) link it into the build system either for a static kernel or as a module; that will come later (after many, many make universe tests.)
439 lines
15 KiB
C
439 lines
15 KiB
C
/*
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* Copyright (c) 2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ar9300/ar9300.h"
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#include "ar9300/ar9300reg.h"
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/*
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* Note: The key cache hardware requires that each double-word
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* pair be written in even/odd order (since the destination is
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* a 64-bit register). Don't reorder the writes in this code
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* w/o considering this!
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*/
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#define KEY_XOR 0xaa
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#define IS_MIC_ENABLED(ah) \
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(AH9300(ah)->ah_sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
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/*
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* This isn't the keytable type; this is actually something separate
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* for the TX descriptor.
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*/
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static const int keyType[] = {
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1, /* HAL_CIPHER_WEP */
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0, /* HAL_CIPHER_AES_OCB */
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2, /* HAL_CIPHER_AES_CCM */
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0, /* HAL_CIPHER_CKIP */
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3, /* HAL_CIPHER_TKIP */
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0 /* HAL_CIPHER_CLR */
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};
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/*
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* Return the size of the hardware key cache.
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*/
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u_int32_t
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ar9300_get_key_cache_size(struct ath_hal *ah)
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{
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return AH_PRIVATE(ah)->ah_caps.halKeyCacheSize;
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}
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/*
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* Return AH_TRUE if the specific key cache entry is valid.
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*/
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HAL_BOOL
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ar9300_is_key_cache_entry_valid(struct ath_hal *ah, u_int16_t entry)
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{
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if (entry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
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u_int32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
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if (val & AR_KEYTABLE_VALID) {
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return AH_TRUE;
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}
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}
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return AH_FALSE;
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}
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/*
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* Clear the specified key cache entry and any associated MIC entry.
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*/
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HAL_BOOL
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ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry)
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{
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u_int32_t key_type;
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struct ath_hal_9300 *ahp = AH9300(ah);
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if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
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"%s: entry %u out of range\n", __func__, entry);
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return AH_FALSE;
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}
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ahp->ah_keytype[entry] = keyType[HAL_CIPHER_CLR];
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key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
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/* XXX why not clear key type/valid bit first? */
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
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if (key_type == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
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u_int16_t micentry = entry + 64; /* MIC goes at slot+64 */
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HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
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/* NB: key type and MAC are known to be ok */
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}
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if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {
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return AH_TRUE;
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}
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if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL)
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== HAL_OK) {
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if (key_type == AR_KEYTABLE_TYPE_TKIP ||
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key_type == AR_KEYTABLE_TYPE_40 ||
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key_type == AR_KEYTABLE_TYPE_104 ||
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key_type == AR_KEYTABLE_TYPE_128) {
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/* SW WAR for Bug 31602 */
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if (--ahp->ah_rifs_sec_cnt == 0) {
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
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"%s: Count = %d, enabling RIFS\n",
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__func__, ahp->ah_rifs_sec_cnt);
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ar9300_set_rifs_delay(ah, AH_TRUE);
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}
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}
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}
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return AH_TRUE;
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}
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/*
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* Sets the mac part of the specified key cache entry (and any
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* associated MIC entry) and mark them valid.
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*/
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HAL_BOOL
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ar9300_set_key_cache_entry_mac(
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struct ath_hal *ah,
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u_int16_t entry,
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const u_int8_t *mac)
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{
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u_int32_t mac_hi, mac_lo;
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u_int32_t unicast_addr = AR_KEYTABLE_VALID;
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if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
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"%s: entry %u out of range\n", __func__, entry);
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return AH_FALSE;
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}
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/*
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* Set MAC address -- shifted right by 1. mac_lo is
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* the 4 MSBs, and mac_hi is the 2 LSBs.
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*/
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if (mac != AH_NULL) {
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/*
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* If upper layers have requested mcast MACaddr lookup, then
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* signify this to the hw by setting the (poorly named) valid_bit
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* to 0. Yes, really 0. The hardware specs, pcu_registers.txt, is
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* has incorrectly named valid_bit. It should be called "Unicast".
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* When the Key Cache entry is to decrypt Unicast frames, this bit
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* should be '1'; for multicast and broadcast frames, this bit is '0'.
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*/
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if (mac[0] & 0x01) {
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unicast_addr = 0; /* Not an unicast address */
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}
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mac_hi = (mac[5] << 8) | mac[4];
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mac_lo = (mac[3] << 24) | (mac[2] << 16)
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| (mac[1] << 8) | mac[0];
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mac_lo >>= 1; /* Note that the bit 0 is shifted out. This bit is used to
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* indicate that this is a multicast key cache. */
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mac_lo |= (mac_hi & 1) << 31; /* carry */
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mac_hi >>= 1;
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} else {
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mac_lo = mac_hi = 0;
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}
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), mac_lo);
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), mac_hi | unicast_addr);
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return AH_TRUE;
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}
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/*
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* Sets the contents of the specified key cache entry
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* and any associated MIC entry.
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*/
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HAL_BOOL
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ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
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const HAL_KEYVAL *k, const u_int8_t *mac,
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int xor_key)
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{
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const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
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u_int32_t key0, key1, key2, key3, key4;
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u_int32_t key_type;
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u_int32_t xor_mask = xor_key ?
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(KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0;
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struct ath_hal_9300 *ahp = AH9300(ah);
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u_int32_t pwrmgt, pwrmgt_mic, uapsd_cfg, psta = 0;
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int is_proxysta_key = k->kv_type & HAL_KEY_PROXY_STA_MASK;
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if (entry >= p_cap->halKeyCacheSize) {
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
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"%s: entry %u out of range\n", __func__, entry);
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return AH_FALSE;
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}
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s[%d] mac %s proxy %d\n",
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__func__, __LINE__, mac ? ath_hal_ether_sprintf(mac) : "null",
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is_proxysta_key);
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switch (k->kv_type & AH_KEYTYPE_MASK) {
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case HAL_CIPHER_AES_OCB:
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key_type = AR_KEYTABLE_TYPE_AES;
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break;
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case HAL_CIPHER_AES_CCM:
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if (!p_cap->halCipherAesCcmSupport) {
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: AES-CCM not supported by "
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"mac rev 0x%x\n",
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__func__, AH_PRIVATE(ah)->ah_macRev);
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return AH_FALSE;
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}
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key_type = AR_KEYTABLE_TYPE_CCM;
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break;
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case HAL_CIPHER_TKIP:
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key_type = AR_KEYTABLE_TYPE_TKIP;
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if (IS_MIC_ENABLED(ah) && entry + 64 >= p_cap->halKeyCacheSize) {
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
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"%s: entry %u inappropriate for TKIP\n",
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__func__, entry);
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return AH_FALSE;
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}
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break;
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case HAL_CIPHER_WEP:
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if (k->kv_len < 40 / NBBY) {
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: WEP key length %u too small\n",
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__func__, k->kv_len);
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return AH_FALSE;
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}
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if (k->kv_len <= 40 / NBBY) {
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key_type = AR_KEYTABLE_TYPE_40;
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} else if (k->kv_len <= 104 / NBBY) {
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key_type = AR_KEYTABLE_TYPE_104;
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} else {
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key_type = AR_KEYTABLE_TYPE_128;
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}
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break;
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case HAL_CIPHER_CLR:
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key_type = AR_KEYTABLE_TYPE_CLR;
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break;
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default:
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: cipher %u not supported\n",
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__func__, k->kv_type);
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return AH_FALSE;
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}
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key0 = LE_READ_4(k->kv_val + 0) ^ xor_mask;
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key1 = (LE_READ_2(k->kv_val + 4) ^ xor_mask) & 0xffff;
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key2 = LE_READ_4(k->kv_val + 6) ^ xor_mask;
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key3 = (LE_READ_2(k->kv_val + 10) ^ xor_mask) & 0xffff;
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key4 = LE_READ_4(k->kv_val + 12) ^ xor_mask;
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if (k->kv_len <= 104 / NBBY) {
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key4 &= 0xff;
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}
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/* Extract the UAPSD AC bits and shift it appropriately */
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uapsd_cfg = k->kv_apsd;
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uapsd_cfg = (u_int32_t) SM(uapsd_cfg, AR_KEYTABLE_UAPSD);
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/* Need to preserve the power management bit used by MAC */
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pwrmgt = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)) & AR_KEYTABLE_PWRMGT;
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if (is_proxysta_key) {
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u_int8_t bcast_mac[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
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if (!mac || OS_MEMCMP(mac, bcast_mac, 6)) {
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psta = AR_KEYTABLE_DIR_ACK_BIT;
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}
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}
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/*
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* Note: key cache hardware requires that each double-word
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* pair be written in even/odd order (since the destination is
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* a 64-bit register). Don't reorder these writes w/o
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* considering this!
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*/
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if (key_type == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
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u_int16_t micentry = entry + 64; /* MIC goes at slot+64 */
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/* Need to preserve the power management bit used by MAC */
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pwrmgt_mic =
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OS_REG_READ(ah, AR_KEYTABLE_TYPE(micentry)) & AR_KEYTABLE_PWRMGT;
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/*
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* Invalidate the encrypt/decrypt key until the MIC
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* key is installed so pending rx frames will fail
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* with decrypt errors rather than a MIC error.
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*/
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
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OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry),
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key_type | pwrmgt | uapsd_cfg | psta);
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ar9300_set_key_cache_entry_mac(ah, entry, mac);
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/*
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* since the AR_MISC_MODE register was written with the contents of
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* ah_misc_mode (if any) in ar9300_attach, just check ah_misc_mode and
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* save a pci read per key set.
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*/
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if (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
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u_int32_t mic0, mic1, mic2, mic3, mic4;
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/*
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* both RX and TX mic values can be combined into
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* one cache slot entry.
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* 8*N + 800 31:0 RX Michael key 0
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* 8*N + 804 15:0 TX Michael key 0 [31:16]
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* 8*N + 808 31:0 RX Michael key 1
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* 8*N + 80C 15:0 TX Michael key 0 [15:0]
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* 8*N + 810 31:0 TX Michael key 1
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* 8*N + 814 15:0 reserved
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* 8*N + 818 31:0 reserved
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* 8*N + 81C 14:0 reserved
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* 15 key valid == 0
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*/
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/* RX mic */
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mic0 = LE_READ_4(k->kv_mic + 0);
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mic2 = LE_READ_4(k->kv_mic + 4);
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/* TX mic */
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mic1 = LE_READ_2(k->kv_txmic + 2) & 0xffff;
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mic3 = LE_READ_2(k->kv_txmic + 0) & 0xffff;
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mic4 = LE_READ_4(k->kv_txmic + 4);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
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OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
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AR_KEYTABLE_TYPE_CLR | pwrmgt_mic | uapsd_cfg);
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} else {
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u_int32_t mic0, mic2;
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mic0 = LE_READ_4(k->kv_mic + 0);
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mic2 = LE_READ_4(k->kv_mic + 4);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
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OS_REG_WRITE(ah,
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AR_KEYTABLE_TYPE(micentry | pwrmgt_mic | uapsd_cfg),
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AR_KEYTABLE_TYPE_CLR);
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}
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/* NB: MIC key is not marked valid and has no MAC address */
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
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OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
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/* correct intentionally corrupted key */
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
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} else {
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
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OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
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OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry),
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key_type | pwrmgt | uapsd_cfg | psta);
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/*
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ath_hal_printf(ah, "%s[%d] mac %s proxy %d\n",
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__func__, __LINE__, mac ? ath_hal_ether_sprintf(mac) : "null",
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is_proxysta_key);
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*/
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ar9300_set_key_cache_entry_mac(ah, entry, mac);
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}
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ahp->ah_keytype[entry] = keyType[k->kv_type];
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: entry=%d, k->kv_type=%d,"
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"keyType=%d\n", __func__, entry, k->kv_type, keyType[k->kv_type]);
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if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {
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return AH_TRUE;
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}
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if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL)
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== HAL_OK) {
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if (key_type == AR_KEYTABLE_TYPE_TKIP ||
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key_type == AR_KEYTABLE_TYPE_40 ||
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key_type == AR_KEYTABLE_TYPE_104 ||
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key_type == AR_KEYTABLE_TYPE_128) {
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/* SW WAR for Bug 31602 */
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ahp->ah_rifs_sec_cnt++;
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
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"%s: Count = %d, disabling RIFS\n",
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__func__, ahp->ah_rifs_sec_cnt);
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ar9300_set_rifs_delay(ah, AH_FALSE);
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}
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}
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HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s[%d] mac %s proxy %d\n",
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__func__, __LINE__, mac ? ath_hal_ether_sprintf(mac) : "null",
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is_proxysta_key);
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return AH_TRUE;
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}
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/*
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* Enable the Keysearch for every subframe of an aggregate
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*/
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void
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ar9300_enable_keysearch_always(struct ath_hal *ah, int enable)
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{
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u_int32_t val;
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if (!ah) {
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return;
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}
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val = OS_REG_READ(ah, AR_PCU_MISC);
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if (enable) {
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val |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
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} else {
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val &= ~AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
|
|
}
|
|
OS_REG_WRITE(ah, AR_PCU_MISC, val);
|
|
}
|
|
void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry)
|
|
{
|
|
#define AH_KEY_REG_SIZE 8
|
|
int i;
|
|
|
|
for (i = 0; i < AH_KEY_REG_SIZE; i++) {
|
|
entry[i] = OS_REG_READ(ah, AR_KEYTABLE_KEY0(n) + i * 4);
|
|
}
|
|
#undef AH_KEY_REG_SIZE
|
|
}
|