45d426a34e
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
262 lines
8.6 KiB
C
262 lines
8.6 KiB
C
/* $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Cache operations.
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*
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* We define the following primitives:
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*
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* --- Instruction cache synchronization (mandatory):
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*
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* icache_sync_all Synchronize I-cache
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*
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* icache_sync_range Synchronize I-cache range
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*
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* icache_sync_range_index (index ops)
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*
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* --- Primary data cache (mandatory):
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*
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* pdcache_wbinv_all Write-back Invalidate primary D-cache
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*
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* pdcache_wbinv_range Write-back Invalidate primary D-cache range
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*
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* pdcache_wbinv_range_index (index ops)
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*
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* pdcache_inv_range Invalidate primary D-cache range
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*
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* pdcache_wb_range Write-back primary D-cache range
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*
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* --- Secondary data cache (optional):
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*
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* sdcache_wbinv_all Write-back Invalidate secondary D-cache
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*
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* sdcache_wbinv_range Write-back Invalidate secondary D-cache range
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*
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* sdcache_wbinv_range_index (index ops)
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*
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* sdcache_inv_range Invalidate secondary D-cache range
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*
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* sdcache_wb_range Write-back secondary D-cache range
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*
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* There are some rules that must be followed:
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*
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* I-cache Synch (all or range):
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* The goal is to synchronize the instruction stream,
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* so you may need to write-back dirty data cache
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* blocks first. If a range is requested, and you
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* can't synchronize just a range, you have to hit
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* the whole thing.
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*
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* D-cache Write-back Invalidate range:
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* If you can't WB-Inv a range, you must WB-Inv the
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* entire D-cache.
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*
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* D-cache Invalidate:
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* If you can't Inv the D-cache without doing a
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* Write-back, YOU MUST PANIC. This is to catch
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* errors in calling code. Callers must be aware
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* of this scenario, and must handle it appropriately
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* (consider the bus_dma(9) operations).
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*
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* D-cache Write-back:
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* If you can't Write-back without doing an invalidate,
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* that's fine. Then treat this as a WB-Inv. Skipping
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* the invalidate is merely an optimization.
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*
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* All operations:
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* Valid virtual addresses must be passed to the
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* cache operation.
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*
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* Finally, these primitives are grouped together in reasonable
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* ways. For all operations described here, first the primary
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* cache is frobbed, then the secondary cache frobbed, if the
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* operation for the secondary cache exists.
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*
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* mips_icache_sync_all Synchronize I-cache
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*
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* mips_icache_sync_range Synchronize I-cache range
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*
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* mips_icache_sync_range_index (index ops)
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*
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* mips_dcache_wbinv_all Write-back Invalidate D-cache
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*
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* mips_dcache_wbinv_range Write-back Invalidate D-cache range
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*
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* mips_dcache_wbinv_range_index (index ops)
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*
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* mips_dcache_inv_range Invalidate D-cache range
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*
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* mips_dcache_wb_range Write-back D-cache range
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*/
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struct mips_cache_ops {
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void (*mco_icache_sync_all)(void);
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void (*mco_icache_sync_range)(vm_offset_t, vm_size_t);
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void (*mco_icache_sync_range_index)(vm_offset_t, vm_size_t);
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void (*mco_pdcache_wbinv_all)(void);
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void (*mco_pdcache_wbinv_range)(vm_offset_t, vm_size_t);
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void (*mco_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
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void (*mco_pdcache_inv_range)(vm_offset_t, vm_size_t);
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void (*mco_pdcache_wb_range)(vm_offset_t, vm_size_t);
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/* These are called only by the (mipsNN) icache functions. */
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void (*mco_intern_pdcache_wbinv_all)(void);
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void (*mco_intern_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
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void (*mco_intern_pdcache_wb_range)(vm_offset_t, vm_size_t);
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void (*mco_sdcache_wbinv_all)(void);
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void (*mco_sdcache_wbinv_range)(vm_offset_t, vm_size_t);
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void (*mco_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
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void (*mco_sdcache_inv_range)(vm_offset_t, vm_size_t);
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void (*mco_sdcache_wb_range)(vm_offset_t, vm_size_t);
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/* These are called only by the (mipsNN) icache functions. */
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void (*mco_intern_sdcache_wbinv_all)(void);
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void (*mco_intern_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
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void (*mco_intern_sdcache_wb_range)(vm_offset_t, vm_size_t);
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};
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extern struct mips_cache_ops mips_cache_ops;
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/* PRIMARY CACHE VARIABLES */
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extern u_int mips_picache_size;
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extern u_int mips_picache_line_size;
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extern u_int mips_picache_ways;
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extern u_int mips_picache_way_size;
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extern u_int mips_picache_way_mask;
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extern u_int mips_pdcache_size; /* and unified */
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extern u_int mips_pdcache_line_size;
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extern u_int mips_pdcache_ways;
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extern u_int mips_pdcache_way_size;
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extern u_int mips_pdcache_way_mask;
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extern int mips_pdcache_write_through;
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extern int mips_pcache_unified;
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/* SECONDARY CACHE VARIABLES */
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extern u_int mips_sicache_size;
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extern u_int mips_sicache_line_size;
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extern u_int mips_sicache_ways;
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extern u_int mips_sicache_way_size;
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extern u_int mips_sicache_way_mask;
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extern u_int mips_sdcache_size; /* and unified */
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extern u_int mips_sdcache_line_size;
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extern u_int mips_sdcache_ways;
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extern u_int mips_sdcache_way_size;
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extern u_int mips_sdcache_way_mask;
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extern int mips_sdcache_write_through;
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extern int mips_scache_unified;
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/* TERTIARY CACHE VARIABLES */
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extern u_int mips_tcache_size; /* always unified */
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extern u_int mips_tcache_line_size;
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extern u_int mips_tcache_ways;
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extern u_int mips_tcache_way_size;
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extern u_int mips_tcache_way_mask;
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extern int mips_tcache_write_through;
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extern u_int mips_dcache_align;
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extern u_int mips_dcache_align_mask;
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extern u_int mips_cache_alias_mask;
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extern u_int mips_cache_prefer_mask;
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#define __mco_noargs(prefix, x) \
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do { \
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(*mips_cache_ops.mco_ ## prefix ## p ## x )(); \
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if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
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(*mips_cache_ops.mco_ ## prefix ## s ## x )(); \
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} while (/*CONSTCOND*/0)
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#define __mco_2args(prefix, x, a, b) \
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do { \
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(*mips_cache_ops.mco_ ## prefix ## p ## x )((a), (b)); \
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if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
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(*mips_cache_ops.mco_ ## prefix ## s ## x )((a), (b)); \
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} while (/*CONSTCOND*/0)
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#define mips_icache_sync_all() \
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(*mips_cache_ops.mco_icache_sync_all)()
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#define mips_icache_sync_range(v, s) \
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(*mips_cache_ops.mco_icache_sync_range)((v), (s))
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#define mips_icache_sync_range_index(v, s) \
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(*mips_cache_ops.mco_icache_sync_range_index)((v), (s))
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#define mips_dcache_wbinv_all() \
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__mco_noargs(, dcache_wbinv_all)
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#define mips_dcache_wbinv_range(v, s) \
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__mco_2args(, dcache_wbinv_range, (v), (s))
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#define mips_dcache_wbinv_range_index(v, s) \
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__mco_2args(, dcache_wbinv_range_index, (v), (s))
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#define mips_dcache_inv_range(v, s) \
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__mco_2args(, dcache_inv_range, (v), (s))
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#define mips_dcache_wb_range(v, s) \
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__mco_2args(, dcache_wb_range, (v), (s))
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/*
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* Private D-cache functions only called from (currently only the
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* mipsNN) I-cache functions.
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*/
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#define mips_intern_dcache_wbinv_all() \
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__mco_noargs(intern_, dcache_wbinv_all)
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#define mips_intern_dcache_wbinv_range_index(v, s) \
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__mco_2args(intern_, dcache_wbinv_range_index, (v), (s))
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#define mips_intern_dcache_wb_range(v, s) \
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__mco_2args(intern_, dcache_wb_range, (v), (s))
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/* forward declaration */
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struct mips_cpuinfo;
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void mips_config_cache(struct mips_cpuinfo *);
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void mips_dcache_compute_align(void);
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#include <machine/cache_mipsNN.h>
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