d6141d33bc
The QCA953x SoC is an integrated 2x2 2GHz 11n + MIPS24k core, with a 5 port FE switch, gige WAN port, and all the same stuff you'd find on its predecessor - the AR9331. However, buried deep in here somewhere is also a PCIe EP/RC for various applications and some other weird bits I don't yet know about. This is enough to get the reference board up and booting. I haven't yet had it pass lots of packets - I need to finalise the ethernet switch bits and the GMAC configuration (ie, how the ethernet ports and switch are wired up) and I'll bring that in when I commit the base configuration files to use the thing. The wifi stuff will come much later. I have to port that support from Linux ath9k and extend our vendor HAL to support it. The reference board (AP143) comes with 32MB RAM and 4MB flash, so in order to use it I need to get USB working fully so I can run root from there. Thankyou to Qualcomm Atheros for access to the reference design board. Details: * Add register definitions from openwrt; * It looks like a QCA955x but shrunk down to a QCA933x footprint, so use the QCA955x bits and fix up the clock detection code to do the QCA953x bits (they're very subtly different); * Teach GPIO about it; * Teach EHCI about it; * Teach if_arge about it; * Teach the CPU detection code about it. Tested: * AP143, QCA9533v2 SoC Obtained from: Linux, Linux OpenWRT
236 lines
6.0 KiB
C
236 lines
6.0 KiB
C
/*-
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* Copyright (c) 2010 Adrian Chadd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <net/ethernet.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <mips/atheros/ar71xxreg.h>
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#include <mips/atheros/ar933xreg.h>
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#include <mips/atheros/ar934xreg.h>
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#include <mips/atheros/qca955xreg.h>
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#include <mips/atheros/qca953xreg.h>
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#include <mips/atheros/ar71xx_setup.h>
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#include <mips/atheros/ar71xx_cpudef.h>
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#include <mips/atheros/ar71xx_chip.h>
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#include <mips/atheros/ar724x_chip.h>
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#include <mips/atheros/ar91xx_chip.h>
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#include <mips/atheros/ar933x_chip.h>
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#include <mips/atheros/ar934x_chip.h>
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#include <mips/atheros/qca953x_chip.h>
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#include <mips/atheros/qca955x_chip.h>
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#define AR71XX_SYS_TYPE_LEN 128
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static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
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enum ar71xx_soc_type ar71xx_soc;
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struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
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void
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ar71xx_detect_sys_type(void)
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{
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char *chip = "????";
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uint32_t id;
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uint32_t major;
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uint32_t minor;
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uint32_t rev = 0;
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id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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switch (major) {
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case REV_ID_MAJOR_AR71XX:
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minor = id & AR71XX_REV_ID_MINOR_MASK;
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rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
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rev &= AR71XX_REV_ID_REVISION_MASK;
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ar71xx_cpu_ops = &ar71xx_chip_def;
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switch (minor) {
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case AR71XX_REV_ID_MINOR_AR7130:
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ar71xx_soc = AR71XX_SOC_AR7130;
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chip = "7130";
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break;
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case AR71XX_REV_ID_MINOR_AR7141:
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ar71xx_soc = AR71XX_SOC_AR7141;
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chip = "7141";
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break;
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case AR71XX_REV_ID_MINOR_AR7161:
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ar71xx_soc = AR71XX_SOC_AR7161;
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chip = "7161";
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break;
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}
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break;
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case REV_ID_MAJOR_AR7240:
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ar71xx_soc = AR71XX_SOC_AR7240;
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chip = "7240";
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ar71xx_cpu_ops = &ar724x_chip_def;
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rev = (id & AR724X_REV_ID_REVISION_MASK);
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break;
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case REV_ID_MAJOR_AR7241:
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ar71xx_soc = AR71XX_SOC_AR7241;
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chip = "7241";
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ar71xx_cpu_ops = &ar724x_chip_def;
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rev = (id & AR724X_REV_ID_REVISION_MASK);
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break;
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case REV_ID_MAJOR_AR7242:
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ar71xx_soc = AR71XX_SOC_AR7242;
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chip = "7242";
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ar71xx_cpu_ops = &ar724x_chip_def;
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rev = (id & AR724X_REV_ID_REVISION_MASK);
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break;
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case REV_ID_MAJOR_AR913X:
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minor = id & AR91XX_REV_ID_MINOR_MASK;
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rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
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rev &= AR91XX_REV_ID_REVISION_MASK;
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ar71xx_cpu_ops = &ar91xx_chip_def;
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switch (minor) {
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case AR91XX_REV_ID_MINOR_AR9130:
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ar71xx_soc = AR71XX_SOC_AR9130;
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chip = "9130";
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break;
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case AR91XX_REV_ID_MINOR_AR9132:
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ar71xx_soc = AR71XX_SOC_AR9132;
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chip = "9132";
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break;
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}
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break;
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case REV_ID_MAJOR_AR9330:
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minor = 0;
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rev = (id & AR933X_REV_ID_REVISION_MASK);
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chip = "9330";
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ar71xx_cpu_ops = &ar933x_chip_def;
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ar71xx_soc = AR71XX_SOC_AR9330;
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break;
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case REV_ID_MAJOR_AR9331:
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minor = 1;
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rev = (id & AR933X_REV_ID_REVISION_MASK);
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chip = "9331";
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ar71xx_soc = AR71XX_SOC_AR9331;
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ar71xx_cpu_ops = &ar933x_chip_def;
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break;
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case REV_ID_MAJOR_AR9341:
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minor = 0;
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rev = (id & AR934X_REV_ID_REVISION_MASK);
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chip = "9341";
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ar71xx_soc = AR71XX_SOC_AR9341;
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ar71xx_cpu_ops = &ar934x_chip_def;
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break;
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case REV_ID_MAJOR_AR9342:
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minor = 0;
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rev = (id & AR934X_REV_ID_REVISION_MASK);
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chip = "9342";
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ar71xx_soc = AR71XX_SOC_AR9342;
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ar71xx_cpu_ops = &ar934x_chip_def;
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break;
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case REV_ID_MAJOR_AR9344:
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minor = 0;
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rev = (id & AR934X_REV_ID_REVISION_MASK);
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chip = "9344";
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ar71xx_soc = AR71XX_SOC_AR9344;
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ar71xx_cpu_ops = &ar934x_chip_def;
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break;
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case REV_ID_MAJOR_QCA9533:
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minor = 0;
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rev = (id & QCA953X_REV_ID_REVISION_MASK);
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chip = "9533";
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ar71xx_soc = AR71XX_SOC_QCA9533;
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ar71xx_cpu_ops = &qca953x_chip_def;
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break;
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case REV_ID_MAJOR_QCA9533_V2:
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minor = 0;
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rev = (id & QCA953X_REV_ID_REVISION_MASK);
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chip = "9533v2";
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ar71xx_soc = AR71XX_SOC_QCA9533_V2;
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ar71xx_cpu_ops = &qca953x_chip_def;
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break;
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case REV_ID_MAJOR_QCA9556:
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minor = 0;
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rev = (id & QCA955X_REV_ID_REVISION_MASK);
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chip = "9556";
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ar71xx_soc = AR71XX_SOC_QCA9556;
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ar71xx_cpu_ops = &qca955x_chip_def;
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break;
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case REV_ID_MAJOR_QCA9558:
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minor = 0;
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rev = (id & QCA955X_REV_ID_REVISION_MASK);
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chip = "9558";
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ar71xx_soc = AR71XX_SOC_QCA9558;
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ar71xx_cpu_ops = &qca955x_chip_def;
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break;
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default:
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panic("ar71xx: unknown chip id:0x%08x\n", id);
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}
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sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
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}
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const char *
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ar71xx_get_system_type(void)
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{
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return ar71xx_sys_type;
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}
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