15b9bcb121
is an application space macro and the applications are supposed to be free to use it as they please (but cannot). This is consistant with the other BSD's who made this change quite some time ago. More commits to come.
256 lines
7.3 KiB
C
256 lines
7.3 KiB
C
/*
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* Copyright 1996 Massachusetts Institute of Technology
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby
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* granted, provided that both the above copyright notice and this
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* permission notice appear in all copies, that both the above
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* copyright notice and this permission notice appear in all
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* supporting documentation, and that the name of M.I.T. not be used
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* in advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission. M.I.T. makes
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* no representations about the suitability of this software for any
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* purpose. It is provided "as is" without express or implied
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* warranty.
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*
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* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
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* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
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* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Interface to performance-monitoring counters for Intel Pentium and
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* Pentium Pro CPUs.
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*/
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#ifndef _MACHINE_PERFMON_H_
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#define _MACHINE_PERFMON_H_
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#ifndef _KERNEL
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#include <sys/types.h>
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#endif
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#include <sys/ioccom.h>
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#define NPMC 2
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#define PMIOSETUP _IOW('5', 1, struct pmc)
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#define PMIOGET _IOWR('5', 7, struct pmc)
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#define PMIOSTART _IOW('5', 2, int)
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#define PMIOSTOP _IOW('5', 3, int)
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#define PMIOREAD _IOWR('5', 4, struct pmc_data)
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#define PMIORESET _IOW('5', 5, int)
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#define PMIOTSTAMP _IOR('5', 6, struct pmc_tstamp)
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struct pmc {
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int pmc_num;
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union {
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struct {
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unsigned char pmcus_event;
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unsigned char pmcus_unit;
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unsigned char pmcus_flags;
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unsigned char pmcus_mask;
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} pmcu_s;
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unsigned int pmcu_val;
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} pmc_pmcu;
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};
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#define PMC_ALL (-1)
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#define pmc_event pmc_pmcu.pmcu_s.pmcus_event
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#define pmc_unit pmc_pmcu.pmcu_s.pmcus_unit
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#define pmc_flags pmc_pmcu.pmcu_s.pmcus_flags
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#define pmc_mask pmc_pmcu.pmcu_s.pmcus_mask
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#define pmc_val pmc_pmcu.pmcu_val
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#define PMCF_USR 0x01 /* count events in user mode */
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#define PMCF_OS 0x02 /* count events in kernel mode */
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#define PMCF_E 0x04 /* use edge-detection mode */
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#define PMCF_PC 0x08 /* PMx output pin control */
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#define PMCF_INT 0x10 /* APIC interrupt enable (do not use) */
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#define PMCF_EN 0x40 /* enable counters */
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#define PMCF_INV 0x80 /* invert counter mask comparison */
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#define PMCF_SYS_FLAGS (PMCF_INT | PMCF_EN) /* user cannot set */
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struct pmc_data {
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int pmcd_num;
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quad_t pmcd_value;
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};
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struct pmc_tstamp {
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int pmct_rate;
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quad_t pmct_value;
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};
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#ifndef _KERNEL
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#define _PATH_PERFMON "/dev/perfmon"
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#else
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/*
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* Intra-kernel interface to performance monitoring counters
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*/
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void perfmon_init __P((void));
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int perfmon_avail __P((void));
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int perfmon_setup __P((int, unsigned int));
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int perfmon_get __P((int, unsigned int *));
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int perfmon_fini __P((int));
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int perfmon_start __P((int));
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int perfmon_stop __P((int));
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int perfmon_read __P((int, quad_t *));
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int perfmon_reset __P((int));
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#endif /* _KERNEL */
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/*
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* Pentium Pro performance counters, from Appendix B.
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*/
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/* Data Cache Unit */
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#define PMC6_DATA_MEM_REFS 0x43
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#define PMC6_DCU_LINES_IN 0x45
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#define PMC6_DCU_M_LINES_IN 0x46
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#define PMC6_DCU_M_LINES_OUT 0x47
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#define PMC6_DCU_MISS_OUTSTANDING 0x48
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/* Instruction Fetch Unit */
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#define PMC6_IFU_IFETCH 0x80
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#define PMC6_IFU_IFETCH_MISS 0x81
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#define PMC6_ITLB_MISS 0x85
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#define PMC6_IFU_MEM_STALL 0x86
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#define PMC6_ILD_STALL 0x87
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/* L2 Cache */
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#define PMC6_L2_IFETCH 0x28 /* MESI */
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#define PMC6_L2_LD 0x29 /* MESI */
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#define PMC6_L2_ST 0x2a /* MESI */
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#define PMC6_L2_LINES_IN 0x24
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#define PMC6_L2_LINES_OUT 0x26
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#define PMC6_L2_M_LINES_INM 0x25
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#define PMC6_L2_M_LINES_OUTM 0x27
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#define PMC6_L2_RQSTS 0x2e /* MESI */
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#define PMC6_L2_ADS 0x21
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#define PMC6_L2_DBUS_BUSY 0x22
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#define PMC6_L2_DBUS_BUSY_RD 0x23
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/* External Bus Logic */
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#define PMC6_BUS_DRDY_CLOCKS 0x62
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#define PMC6_BUS_LOCK_CLOCKS 0x63
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#define PMC6_BUS_REQ_OUTSTANDING 0x60
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#define PMC6_BUS_TRAN_BRD 0x65
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#define PMC6_BUS_TRAN_RFO 0x66
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#define PMC6_BUS_TRAN_WB 0x67
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#define PMC6_BUS_TRAN_IFETCH 0x68
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#define PMC6_BUS_TRAN_INVAL 0x69
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#define PMC6_BUS_TRAN_PWR 0x6a
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#define PMC6_BUS_TRAN_P 0x6b
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#define PMC6_BUS_TRAN_IO 0x6c
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#define PMC6_BUS_TRAN_DEF 0x6d
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#define PMC6_BUS_TRAN_BURST 0x6e
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#define PMC6_BUS_TRAN_ANY 0x70
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#define PMC6_BUS_TRAN_MEM 0x6f
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#define PMC6_BUS_DATA_RCV 0x64
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#define PMC6_BUS_BNR_DRV 0x61
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#define PMC6_BUS_HIT_DRV 0x7a
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#define PMC6_BUS_HITM_DRV 0x7b
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#define PMC6_BUS_SNOOP_STALL 0x7e
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/* Floating Point Unit */
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#define PMC6_FLOPS 0xc1 /* counter 0 only */
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#define PMC6_FP_COMP_OPS_EXE 0x10 /* counter 0 only */
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#define PMC6_FP_ASSIST 0x11 /* counter 1 only */
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#define PMC6_MUL 0x12 /* counter 1 only */
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#define PMC6_DIV 0x13 /* counter 1 only */
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#define PMC6_CYCLES_DIV_BUSY 0x14 /* counter 0 only */
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/* Memory Ordering */
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#define PMC6_LD_BLOCKS 0x03
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#define PMC6_SB_DRAINS 0x04
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#define PMC6_MISALIGN_MEM_REF 0x05
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/* Instruction Decoding and Retirement */
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#define PMC6_INST_RETIRED 0xc0
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#define PMC6_UOPS_RETIRED 0xc2
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#define PMC6_INST_DECODER 0xd0 /* (sic) */
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/* Interrupts */
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#define PMC6_HW_INT_RX 0xc8
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#define PMC6_CYCLES_INT_MASKED 0xc6
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#define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
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/* Branches */
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#define PMC6_BR_INST_RETIRED 0xc4
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#define PMC6_BR_MISS_PRED_RETIRED 0xc5
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#define PMC6_BR_TAKEN_RETIRED 0xc9
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#define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
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#define PMC6_BR_INST_DECODED 0xe0
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#define PMC6_BTB_MISSES 0xe2
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#define PMC6_BR_BOGUS 0xe4
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#define PMC6_BACLEARS 0xe6
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/* Stalls */
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#define PMC6_RESOURCE_STALLS 0xa2
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#define PMC6_PARTIAL_RAT_STALLS 0xd2
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/* Segment Register Loads */
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#define PMC6_SEGMENT_REG_LOADS 0x06
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/* Clocks */
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#define PMC6_CPU_CLK_UNHALTED 0x79
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/*
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* Pentium Performance Counters
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* This list comes from the Harvard people, not Intel.
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*/
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#define PMC5_DATA_READ 0
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#define PMC5_DATA_WRITE 1
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#define PMC5_DATA_TLB_MISS 2
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#define PMC5_DATA_READ_MISS 3
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#define PMC5_DATA_WRITE_MISS 4
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#define PMC5_WRITE_M_E 5
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#define PMC5_DATA_LINES_WBACK 6
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#define PMC5_DATA_CACHE_SNOOP 7
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#define PMC5_DATA_CACHE_SNOOP_HIT 8
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#define PMC5_MEM_ACCESS_BOTH 9
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#define PMC5_BANK_CONFLICTS 10
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#define PMC5_MISALIGNED_DATA 11
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#define PMC5_INST_READ 12
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#define PMC5_INST_TLB_MISS 13
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#define PMC5_INST_CACHE_MISS 14
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#define PMC5_SEGMENT_REG_LOAD 15
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#define PMC5_BRANCHES 18
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#define PMC5_BTB_HITS 19
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#define PMC5_BRANCH_TAKEN 20
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#define PMC5_PIPELINE_FLUSH 21
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#define PMC5_INST_EXECUTED 22
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#define PMC5_INST_EXECUTED_V 23
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#define PMC5_BUS_UTILIZATION 24
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#define PMC5_WRITE_BACKUP_STALL 25
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#define PMC5_DATA_READ_STALL 26
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#define PMC5_WRITE_E_M_STALL 27
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#define PMC5_LOCKED_BUS 28
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#define PMC5_IO_CYCLE 29
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#define PMC5_NONCACHE_MEMORY 30
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#define PMC5_ADDR_GEN_INTERLOCK 31
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#define PMC5_FLOPS 34
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#define PMC5_BP0_MATCH 35
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#define PMC5_BP1_MATCH 36
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#define PMC5_BP2_MATCH 37
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#define PMC5_BP3_MATCH 38
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#define PMC5_HW_INTR 39
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#define PMC5_DATA_RW 40
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#define PMC5_DATA_RW_MISS 41
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#endif /* !_MACHINE_PERFMON_H_ */
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