50a9f1c71c
This fine work was done by Yohanes Nugroho <yohanes a gmail dot com> Many thanks to John Nicholls and Thinlinx for providing sample hardware.
52 lines
2.5 KiB
C
52 lines
2.5 KiB
C
/*-
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* Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_AICREG_H
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#define ARM_AT91_AT91_AICREG_H
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/* Interrupt Controller */
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#define IC_SMR (0) /* Source mode register */
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#define IC_SVR (128) /* Source vector register */
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#define IC_IVR (256) /* IRQ vector register */
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#define IC_FVR (260) /* FIQ vector register */
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#define IC_ISR (264) /* Interrupt status register */
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#define IC_IPR (268) /* Interrupt pending register */
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#define IC_IMR (272) /* Interrupt status register */
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#define IC_CISR (276) /* Core interrupt status register */
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#define IC_IECR (288) /* Interrupt enable command register */
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#define IC_IDCR (292) /* Interrupt disable command register */
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#define IC_ICCR (296) /* Interrupt clear command register */
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#define IC_ISCR (300) /* Interrupt set command register */
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#define IC_EOICR (304) /* End of interrupt command register */
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#define IC_SPU (308) /* Spurious vector register */
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#define IC_DCR (312) /* Debug control register */
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#define IC_FFER (320) /* Fast forcing enable register */
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#define IC_FFDR (324) /* Fast forcing disable register */
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#define IC_FFSR (328) /* Fast forcing status register */
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#endif /*ARM_AT91_AT91_AICREG_H*/
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