George V. Neville-Neil 660df75e8b Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor. ... Add macros for properly accessing coprocessor 0 registers that support performance counters. Reviewed by: jkoshy rpaulo fabien imp MFC after: 1 month		2010-03-03 15:05:58 +00:00
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hwpmc_amd.c
hwpmc_amd.h
hwpmc_arm.c
hwpmc_core.c	* Support the L1D_CACHE_LD event on Core2 processors.	2009-12-26 14:39:23 +00:00
hwpmc_core.h
hwpmc_ia64.c
hwpmc_intel.c
hwpmc_logging.c
hwpmc_mips24k.c	Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.	2010-03-03 15:05:58 +00:00
hwpmc_mips24k.h	Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.	2010-03-03 15:05:58 +00:00
hwpmc_mips.c	Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.	2010-03-03 15:05:58 +00:00
hwpmc_mod.c	Use VFS_{LOCK,UNLOCK}_GIANT() around the call to vrele().	2009-12-29 02:35:50 +00:00
hwpmc_pentium.c
hwpmc_pentium.h
hwpmc_piv.c
hwpmc_piv.h
hwpmc_powerpc.c
hwpmc_ppro.c
hwpmc_ppro.h
hwpmc_sparc64.c
hwpmc_tsc.c
hwpmc_tsc.h
hwpmc_x86.c
hwpmc_xscale.c
hwpmc_xscale.h
pmc_events.h	Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.	2010-03-03 15:05:58 +00:00