6bb1cadd56
that builds the following additional llvm/clang tools: - bugpoint - llc - lli - llvm-ar - llvm-as - llvm-bcanalyzer - llvm-diff - llvm-dis - llvm-extract - llvm-ld - llvm-link - llvm-mc - llvm-nm - llvm-objdump - llvm-prof - llvm-ranlib - llvm-rtdyld - llvm-stub - macho-dump - opt These tools are mainly useful for people that want to manipulate llvm bitcode (.bc) and llvm assembly language (.ll) files, or want to tinker with llvm and clang themselves. MFC after: 2 weeks
286 lines
9.9 KiB
Groff
286 lines
9.9 KiB
Groff
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.\" ========================================================================
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.\"
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.IX Title "LLC 1"
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.TH LLC 1 "2011-10-17" "LLVM 3.0" "LLVM Command Guide"
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.\" For nroff, turn off justification. Always turn off hyphenation; it makes
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.\" way too many mistakes in technical documents.
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.if n .ad l
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.nh
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.SH "NAME"
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llc \- LLVM static compiler
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.SH "SYNOPSIS"
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.IX Header "SYNOPSIS"
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\&\fBllc\fR [\fIoptions\fR] [\fIfilename\fR]
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.SH "DESCRIPTION"
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.IX Header "DESCRIPTION"
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The \fBllc\fR command compiles \s-1LLVM\s0 source inputs into assembly language for a
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specified architecture. The assembly language output can then be passed through
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a native assembler and linker to generate a native executable.
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.PP
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The choice of architecture for the output assembly code is automatically
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determined from the input file, unless the \fB\-march\fR option is used to override
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the default.
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.SH "OPTIONS"
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.IX Header "OPTIONS"
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If \fIfilename\fR is \- or omitted, \fBllc\fR reads from standard input. Otherwise, it
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will from \fIfilename\fR. Inputs can be in either the \s-1LLVM\s0 assembly language
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format (.ll) or the \s-1LLVM\s0 bitcode format (.bc).
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.PP
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If the \fB\-o\fR option is omitted, then \fBllc\fR will send its output to standard
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output if the input is from standard input. If the \fB\-o\fR option specifies \-,
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then the output will also be sent to standard output.
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.PP
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If no \fB\-o\fR option is specified and an input file other than \- is specified,
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then \fBllc\fR creates the output filename by taking the input filename,
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removing any existing \fI.bc\fR extension, and adding a \fI.s\fR suffix.
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.PP
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Other \fBllc\fR options are as follows:
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.SS "End-user Options"
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.IX Subsection "End-user Options"
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.IP "\fB\-help\fR" 4
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.IX Item "-help"
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Print a summary of command line options.
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.IP "\fB\-O\fR=\fIuint\fR" 4
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.IX Item "-O=uint"
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Generate code at different optimization levels. These correspond to the \fI\-O0\fR,
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\&\fI\-O1\fR, \fI\-O2\fR, \fI\-O3\fR, and \fI\-O4\fR optimization levels used by \fBllvm-gcc\fR and
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\&\fBclang\fR.
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.IP "\fB\-mtriple\fR=\fItarget triple\fR" 4
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.IX Item "-mtriple=target triple"
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Override the target triple specified in the input file with the specified
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string.
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.IP "\fB\-march\fR=\fIarch\fR" 4
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.IX Item "-march=arch"
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Specify the architecture for which to generate assembly, overriding the target
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encoded in the input file. See the output of \fBllc \-help\fR for a list of
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valid architectures. By default this is inferred from the target triple or
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autodetected to the current architecture.
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.IP "\fB\-mcpu\fR=\fIcpuname\fR" 4
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.IX Item "-mcpu=cpuname"
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Specify a specific chip in the current architecture to generate code for.
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By default this is inferred from the target triple and autodetected to
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the current architecture. For a list of available CPUs, use:
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\&\fBllvm-as < /dev/null | llc \-march=xyz \-mcpu=help\fR
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.IP "\fB\-mattr\fR=\fIa1,+a2,\-a3,...\fR" 4
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.IX Item "-mattr=a1,+a2,-a3,..."
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Override or control specific attributes of the target, such as whether \s-1SIMD\s0
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operations are enabled or not. The default set of attributes is set by the
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current \s-1CPU\s0. For a list of available attributes, use:
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\&\fBllvm-as < /dev/null | llc \-march=xyz \-mattr=help\fR
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.IP "\fB\-\-disable\-fp\-elim\fR" 4
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.IX Item "--disable-fp-elim"
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Disable frame pointer elimination optimization.
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.IP "\fB\-\-disable\-excess\-fp\-precision\fR" 4
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.IX Item "--disable-excess-fp-precision"
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Disable optimizations that may produce excess precision for floating point.
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Note that this option can dramatically slow down code on some systems
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(e.g. X86).
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.IP "\fB\-\-enable\-no\-infs\-fp\-math\fR" 4
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.IX Item "--enable-no-infs-fp-math"
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Enable optimizations that assume no Inf values.
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.IP "\fB\-\-enable\-no\-nans\-fp\-math\fR" 4
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.IX Item "--enable-no-nans-fp-math"
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Enable optimizations that assume no \s-1NAN\s0 values.
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.IP "\fB\-\-enable\-unsafe\-fp\-math\fR" 4
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.IX Item "--enable-unsafe-fp-math"
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Enable optimizations that make unsafe assumptions about \s-1IEEE\s0 math (e.g. that
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addition is associative) or may not work for all input ranges. These
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optimizations allow the code generator to make use of some instructions which
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would otherwise not be usable (such as fsin on X86).
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.IP "\fB\-\-enable\-correct\-eh\-support\fR" 4
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.IX Item "--enable-correct-eh-support"
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Instruct the \fBlowerinvoke\fR pass to insert code for correct exception handling
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support. This is expensive and is by default omitted for efficiency.
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.IP "\fB\-\-stats\fR" 4
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.IX Item "--stats"
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Print statistics recorded by code-generation passes.
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.IP "\fB\-\-time\-passes\fR" 4
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.IX Item "--time-passes"
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Record the amount of time needed for each pass and print a report to standard
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error.
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.IP "\fB\-\-load\fR=\fIdso_path\fR" 4
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.IX Item "--load=dso_path"
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Dynamically load \fIdso_path\fR (a path to a dynamically shared object) that
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implements an \s-1LLVM\s0 target. This will permit the target name to be used with the
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\&\fB\-march\fR option so that code can be generated for that target.
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.SS "Tuning/Configuration Options"
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.IX Subsection "Tuning/Configuration Options"
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.IP "\fB\-\-print\-machineinstrs\fR" 4
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.IX Item "--print-machineinstrs"
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Print generated machine code between compilation phases (useful for debugging).
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.IP "\fB\-\-regalloc\fR=\fIallocator\fR" 4
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.IX Item "--regalloc=allocator"
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Specify the register allocator to use. The default \fIallocator\fR is \fIlocal\fR.
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Valid register allocators are:
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.RS 4
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.IP "\fIsimple\fR" 4
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.IX Item "simple"
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Very simple \*(L"always spill\*(R" register allocator
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.IP "\fIlocal\fR" 4
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.IX Item "local"
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Local register allocator
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.IP "\fIlinearscan\fR" 4
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.IX Item "linearscan"
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Linear scan global register allocator
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.IP "\fIiterativescan\fR" 4
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.IX Item "iterativescan"
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Iterative scan global register allocator
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.RE
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.RS 4
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.RE
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.IP "\fB\-\-spiller\fR=\fIspiller\fR" 4
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.IX Item "--spiller=spiller"
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Specify the spiller to use for register allocators that support it. Currently
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this option is used only by the linear scan register allocator. The default
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\&\fIspiller\fR is \fIlocal\fR. Valid spillers are:
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.RS 4
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.IP "\fIsimple\fR" 4
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.IX Item "simple"
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Simple spiller
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.IP "\fIlocal\fR" 4
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.IX Item "local"
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Local spiller
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.RE
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.RS 4
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.RE
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.SS "Intel IA\-32\-specific Options"
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.IX Subsection "Intel IA-32-specific Options"
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.IP "\fB\-\-x86\-asm\-syntax=att|intel\fR" 4
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.IX Item "--x86-asm-syntax=att|intel"
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Specify whether to emit assembly code in \s-1AT&T\s0 syntax (the default) or intel
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syntax.
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.SH "EXIT STATUS"
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.IX Header "EXIT STATUS"
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If \fBllc\fR succeeds, it will exit with 0. Otherwise, if an error occurs,
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it will exit with a non-zero value.
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.SH "SEE ALSO"
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.IX Header "SEE ALSO"
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lli
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.SH "AUTHORS"
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.IX Header "AUTHORS"
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Maintained by the \s-1LLVM\s0 Team (<http://llvm.org/>).
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