9accef3f0f
Major changes:
- Add i219/i219(2) hardware support. (Found on Skylake generation and newer
chipsets.)
- Further to the last Skylake support diff, this one also includes support for
the Lewisburg chipset (i219(3)).
- Add a workaround to an igb hardware errata.
All 1G server products need to have IPv6 extension header parsing turned off.
This should be listed in the specification updates for current 1G server
products, e.g. for i350 it's errata #37 in this document:
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ethernet-controller-i350-spec-update.pdf
- Avoton (i354) PHY errata workaround added
And a bunch of minor fixes, as well as #defines for things that the current
em(4)/igb(4) drivers don't implement.
Differential Revision: https://reviews.freebsd.org/D3162
Reviewed by: sbruno, marius, gnn
Approved by: gnn
MFC after: 2 weeks
Sponsored by: Intel Corporation
559 lines
18 KiB
C
559 lines
18 KiB
C
/******************************************************************************
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Copyright (c) 2001-2015, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _EM_H_DEFINED_
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#define _EM_H_DEFINED_
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/* Tunables */
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/*
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* EM_TXD: Maximum number of Transmit Descriptors
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* Valid Range: 80-256 for 82542 and 82543-based adapters
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* 80-4096 for others
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* Default Value: 256
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* This value is the number of transmit descriptors allocated by the driver.
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* Increasing this value allows the driver to queue more transmits. Each
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* descriptor is 16 bytes.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define EM_MIN_TXD 80
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#define EM_MAX_TXD 4096
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#ifdef EM_MULTIQUEUE
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#define EM_DEFAULT_TXD 4096
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#else
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#define EM_DEFAULT_TXD 1024
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#endif
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/*
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* EM_RXD - Maximum number of receive Descriptors
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* Valid Range: 80-256 for 82542 and 82543-based adapters
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* 80-4096 for others
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* Default Value: 256
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* This value is the number of receive descriptors allocated by the driver.
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* Increasing this value allows the driver to buffer more incoming packets.
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* Each descriptor is 16 bytes. A receive buffer is also allocated for each
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* descriptor. The maximum MTU size is 16110.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define EM_MIN_RXD 80
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#define EM_MAX_RXD 4096
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#ifdef EM_MULTIQUEUE
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#define EM_DEFAULT_RXD 4096
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#else
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#define EM_DEFAULT_RXD 1024
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#endif
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/*
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* EM_TIDV - Transmit Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value delays the generation of transmit interrupts in units of
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* 1.024 microseconds. Transmit interrupt reduction can improve CPU
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* efficiency if properly tuned for specific network traffic. If the
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* system is reporting dropped transmits, this value may be set too high
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* causing the driver to run out of available transmit descriptors.
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*/
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#define EM_TIDV 64
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/*
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* EM_TADV - Transmit Absolute Interrupt Delay Value
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* (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is sent on the wire within the set amount of time. Proper tuning,
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* along with EM_TIDV, may improve traffic throughput in specific
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* network conditions.
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*/
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#define EM_TADV 64
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/*
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* EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 0
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* This value delays the generation of receive interrupts in units of 1.024
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* microseconds. Receive interrupt reduction can improve CPU efficiency if
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* properly tuned for specific network traffic. Increasing this value adds
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* extra latency to frame reception and can end up decreasing the throughput
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* of TCP traffic. If the system is reporting dropped receives, this value
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* may be set too high, causing the driver to run out of available receive
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* descriptors.
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*
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* CAUTION: When setting EM_RDTR to a value other than 0, adapters
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* may hang (stop transmitting) under certain network conditions.
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* If this occurs a WATCHDOG message is logged in the system
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* event log. In addition, the controller is automatically reset,
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* restoring the network connection. To eliminate the potential
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* for the hang ensure that EM_RDTR is set to 0.
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*/
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#ifdef EM_MULTIQUEUE
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#define EM_RDTR 64
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#else
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#define EM_RDTR 0
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#endif
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/*
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* Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* receive interrupt is generated. Useful only if EM_RDTR is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is received within the set amount of time. Proper tuning,
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* along with EM_RDTR, may improve traffic throughput in specific network
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* conditions.
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*/
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#ifdef EM_MULTIQUEUE
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#define EM_RADV 128
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#else
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#define EM_RADV 64
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#endif
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/*
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* This parameter controls the max duration of transmit watchdog.
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*/
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#define EM_WATCHDOG (10 * hz)
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/*
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* This parameter controls when the driver calls the routine to reclaim
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* transmit descriptors.
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*/
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#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
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/*
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* This parameter controls whether or not autonegotation is enabled.
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* 0 - Disable autonegotiation
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* 1 - Enable autonegotiation
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*/
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#define DO_AUTO_NEG 1
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/*
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* This parameter control whether or not the driver will wait for
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* autonegotiation to complete.
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* 1 - Wait for autonegotiation to complete
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* 0 - Don't wait for autonegotiation to complete
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*/
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#define WAIT_FOR_AUTO_NEG_DEFAULT 0
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/* Tunables -- End */
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#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
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ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
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ADVERTISE_1000_FULL)
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#define AUTO_ALL_MODES 0
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/* PHY master/slave setting */
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#define EM_MASTER_SLAVE e1000_ms_hw_default
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/*
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* Micellaneous constants
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*/
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#define EM_VENDOR_ID 0x8086
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#define EM_FLASH 0x0014
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#define EM_JUMBO_PBA 0x00000028
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#define EM_DEFAULT_PBA 0x00000030
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#define EM_SMARTSPEED_DOWNSHIFT 3
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#define EM_SMARTSPEED_MAX 15
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#define EM_MAX_LOOP 10
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#define MAX_NUM_MULTICAST_ADDRESSES 128
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#define PCI_ANY_ID (~0U)
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#define ETHER_ALIGN 2
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#define EM_FC_PAUSE_TIME 0x0680
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#define EM_EEPROM_APME 0x400;
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#define EM_82544_APME 0x0004;
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/*
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* Driver state logic for the detection of a hung state
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* in hardware. Set TX_HUNG whenever a TX packet is used
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* (data is sent) and clear it when txeof() is invoked if
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* any descriptors from the ring are cleaned/reclaimed.
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* Increment internal counter if no descriptors are cleaned
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* and compare to TX_MAXTRIES. When counter > TX_MAXTRIES,
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* reset adapter.
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*/
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#define EM_TX_IDLE 0x00000000
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#define EM_TX_BUSY 0x00000001
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#define EM_TX_HUNG 0x80000000
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#define EM_TX_MAXTRIES 10
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#define PCICFG_DESC_RING_STATUS 0xe4
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#define FLUSH_DESC_REQUIRED 0x100
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/*
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* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
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* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
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* also optimize cache line size effect. H/W supports up to cache line size 128.
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*/
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#define EM_DBA_ALIGN 128
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/*
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* See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9
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*/
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#define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */
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#define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
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#define TARC_MQ_FIX (1 << 23) | \
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(1 << 24) | \
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(1 << 25) /* Handle errata in MQ mode */
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#define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */
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/* PCI Config defines */
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#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
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#define EM_BAR_TYPE_MASK 0x00000001
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#define EM_BAR_TYPE_MMEM 0x00000000
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#define EM_BAR_TYPE_FLASH 0x0014
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#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
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#define EM_BAR_MEM_TYPE_MASK 0x00000006
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#define EM_BAR_MEM_TYPE_32BIT 0x00000000
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#define EM_BAR_MEM_TYPE_64BIT 0x00000004
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#define EM_MSIX_BAR 3 /* On 82575 */
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/* More backward compatibility */
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#if __FreeBSD_version < 900000
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#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
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#endif
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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#define DEBUG_IOCTL 0
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#define DEBUG_HW 0
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#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
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#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
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#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
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#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
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#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
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#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
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#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
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#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
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#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
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#define EM_MAX_SCATTER 64
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#define EM_VFTA_SIZE 128
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#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
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#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
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#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
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#define EM_MSIX_LINK 0x01000000 /* For 82574 use */
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#define ETH_ZLEN 60
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#define ETH_ADDR_LEN 6
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#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
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/*
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* 82574 has a nonstandard address for EIAC
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* and since its only used in MSIX, and in
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* the em driver only 82574 uses MSIX we can
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* solve it just using this define.
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*/
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#define EM_EIAC 0x000DC
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/*
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* 82574 only reports 3 MSI-X vectors by default;
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* defines assisting with making it report 5 are
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* located here.
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*/
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#define EM_NVM_PCIE_CTRL 0x1B
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#define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT)
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#define EM_NVM_MSIX_N_SHIFT 7
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/*
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* Bus dma allocation structure used by
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* e1000_dma_malloc and e1000_dma_free.
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*/
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struct em_dma_alloc {
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bus_addr_t dma_paddr;
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caddr_t dma_vaddr;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_dma_segment_t dma_seg;
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int dma_nseg;
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};
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struct adapter;
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struct em_int_delay_info {
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struct adapter *adapter; /* Back-pointer to the adapter struct */
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int offset; /* Register offset to read/write */
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int value; /* Current value in usecs */
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};
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/*
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* The transmit ring, one per tx queue
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*/
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struct tx_ring {
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struct adapter *adapter;
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struct mtx tx_mtx;
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char mtx_name[16];
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u32 me;
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u32 msix;
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u32 ims;
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int busy;
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struct em_dma_alloc txdma;
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struct e1000_tx_desc *tx_base;
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struct task tx_task;
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struct taskqueue *tq;
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u32 next_avail_desc;
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u32 next_to_clean;
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struct em_txbuffer *tx_buffers;
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volatile u16 tx_avail;
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u32 tx_tso; /* last tx was tso */
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u16 last_hw_offload;
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u8 last_hw_ipcso;
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u8 last_hw_ipcss;
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u8 last_hw_tucso;
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u8 last_hw_tucss;
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#if __FreeBSD_version >= 800000
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struct buf_ring *br;
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#endif
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/* Interrupt resources */
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bus_dma_tag_t txtag;
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void *tag;
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struct resource *res;
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unsigned long tx_irq;
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unsigned long no_desc_avail;
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};
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/*
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* The Receive ring, one per rx queue
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*/
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struct rx_ring {
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struct adapter *adapter;
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u32 me;
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u32 msix;
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u32 ims;
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struct mtx rx_mtx;
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char mtx_name[16];
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u32 payload;
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struct task rx_task;
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struct taskqueue *tq;
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union e1000_rx_desc_extended *rx_base;
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struct em_dma_alloc rxdma;
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u32 next_to_refresh;
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u32 next_to_check;
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struct em_rxbuffer *rx_buffers;
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struct mbuf *fmp;
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struct mbuf *lmp;
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/* Interrupt resources */
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void *tag;
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struct resource *res;
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bus_dma_tag_t rxtag;
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bool discard;
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/* Soft stats */
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unsigned long rx_irq;
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unsigned long rx_discarded;
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unsigned long rx_packets;
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unsigned long rx_bytes;
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};
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/* Our adapter structure */
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struct adapter {
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if_t ifp;
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struct e1000_hw hw;
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/* FreeBSD operating-system-specific structures. */
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struct e1000_osdep osdep;
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struct device *dev;
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struct cdev *led_dev;
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struct resource *memory;
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struct resource *flash;
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struct resource *msix_mem;
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struct resource *res;
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void *tag;
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u32 linkvec;
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u32 ivars;
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struct ifmedia media;
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struct callout timer;
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int msix;
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int if_flags;
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int max_frame_size;
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int min_frame_size;
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struct mtx core_mtx;
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int em_insert_vlan_header;
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u32 ims;
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bool in_detach;
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/* Task for FAST handling */
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struct task link_task;
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struct task que_task;
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struct taskqueue *tq; /* private task queue */
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eventhandler_tag vlan_attach;
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eventhandler_tag vlan_detach;
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u16 num_vlans;
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u8 num_queues;
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/*
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* Transmit rings:
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* Allocated at run time, an array of rings.
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*/
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struct tx_ring *tx_rings;
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int num_tx_desc;
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u32 txd_cmd;
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/*
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* Receive rings:
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* Allocated at run time, an array of rings.
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*/
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struct rx_ring *rx_rings;
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int num_rx_desc;
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u32 rx_process_limit;
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u32 rx_mbuf_sz;
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/* Management and WOL features */
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u32 wol;
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bool has_manage;
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bool has_amt;
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/* Multicast array memory */
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u8 *mta;
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/*
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** Shadow VFTA table, this is needed because
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** the real vlan filter table gets cleared during
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** a soft reset and the driver needs to be able
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** to repopulate it.
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*/
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u32 shadow_vfta[EM_VFTA_SIZE];
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/* Info about the interface */
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u16 link_active;
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u16 fc;
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u16 link_speed;
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u16 link_duplex;
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u32 smartspeed;
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struct em_int_delay_info tx_int_delay;
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struct em_int_delay_info tx_abs_int_delay;
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struct em_int_delay_info rx_int_delay;
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struct em_int_delay_info rx_abs_int_delay;
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struct em_int_delay_info tx_itr;
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/* Misc stats maintained by the driver */
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unsigned long dropped_pkts;
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unsigned long link_irq;
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unsigned long mbuf_defrag_failed;
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unsigned long no_tx_dma_setup;
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unsigned long no_tx_map_avail;
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unsigned long rx_overruns;
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unsigned long watchdog_events;
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struct e1000_hw_stats stats;
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};
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/********************************************************************************
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* vendor_info_array
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*
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* This array contains the list of Subvendor/Subdevice IDs on which the driver
|
|
* should load.
|
|
*
|
|
********************************************************************************/
|
|
typedef struct _em_vendor_info_t {
|
|
unsigned int vendor_id;
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|
unsigned int device_id;
|
|
unsigned int subvendor_id;
|
|
unsigned int subdevice_id;
|
|
unsigned int index;
|
|
} em_vendor_info_t;
|
|
|
|
struct em_txbuffer {
|
|
int next_eop; /* Index of the desc to watch */
|
|
struct mbuf *m_head;
|
|
bus_dmamap_t map; /* bus_dma map for packet */
|
|
};
|
|
|
|
struct em_rxbuffer {
|
|
int next_eop; /* Index of the desc to watch */
|
|
struct mbuf *m_head;
|
|
bus_dmamap_t map; /* bus_dma map for packet */
|
|
bus_addr_t paddr;
|
|
};
|
|
|
|
|
|
/*
|
|
** Find the number of unrefreshed RX descriptors
|
|
*/
|
|
static inline u16
|
|
e1000_rx_unrefreshed(struct rx_ring *rxr)
|
|
{
|
|
struct adapter *adapter = rxr->adapter;
|
|
|
|
if (rxr->next_to_check > rxr->next_to_refresh)
|
|
return (rxr->next_to_check - rxr->next_to_refresh - 1);
|
|
else
|
|
return ((adapter->num_rx_desc + rxr->next_to_check) -
|
|
rxr->next_to_refresh - 1);
|
|
}
|
|
|
|
#define EM_CORE_LOCK_INIT(_sc, _name) \
|
|
mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
|
|
#define EM_TX_LOCK_INIT(_sc, _name) \
|
|
mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
|
|
#define EM_RX_LOCK_INIT(_sc, _name) \
|
|
mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
|
|
#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
|
|
#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
|
|
#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
|
|
#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
|
|
#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
|
|
#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
|
|
#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
|
|
#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
|
|
#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
|
|
#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
|
|
#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
|
|
#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
|
|
#define EM_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED)
|
|
|
|
#define EM_RSSRK_SIZE 4
|
|
#define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \
|
|
key[(i) * EM_RSSRK_SIZE + 1] << 8 | \
|
|
key[(i) * EM_RSSRK_SIZE + 2] << 16 | \
|
|
key[(i) * EM_RSSRK_SIZE + 3] << 24)
|
|
#endif /* _EM_H_DEFINED_ */
|