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of hardware. Mostly this focuses on the big changes needed for setting the bus clock, because ESDHC is SDHCI v2.0 and USDHC is 3.0, and the number, location, and interpretation of clock divisor bits is vastly different between the two. This doesn't get the device all the way to functioning on ESDHC hardware yet, but it's much closer, now getting through all the card detection and negotiation of capabilties and speed (but it eventually hangs on what appears to be a missing interrupt). Another missing chunk of code for handling ESDHC's 32 bit command-and-mode register using sdhci's pair of 16 bit writes is added. This also does some leading whitespace cleanups and sorts some softc struct members by size, and adds some comments (because when do I ever touch code without adding comments?).
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