73703ef8b3
> Description of fields to fill in above: 76 columns --| > PR: If a GNATS PR is affected by the change. > Submitted by: If someone else sent in the change. > Reviewed by: If someone else reviewed your modification. > Approved by: If you needed approval for this commit. > Obtained from: If the change is from a third party. > MFC after: N [day[s]|week[s]|month[s]]. Request a reminder email. > Security: Vulnerability reference (one per line) or description. > Empty fields above will be automatically removed. M rmi/xls_ehci.c M rmi/clock.h M rmi/xlr_pci.c M rmi/perfmon.h M rmi/uart_bus_xlr_iodi.c M rmi/perfmon_percpu.c M rmi/iodi.c M rmi/pcibus.c M rmi/perfmon_kern.c M rmi/perfmon_xlrconfig.h M rmi/pcibus.h M rmi/tick.c M rmi/xlr_boot1_console.c M rmi/debug.h M rmi/uart_cpu_mips_xlr.c M rmi/xlrconfig.h M rmi/interrupt.h M rmi/xlr_i2c.c M rmi/shared_structs.h M rmi/msgring.c M rmi/iomap.h M rmi/ehcireg.h M rmi/msgring.h M rmi/shared_structs_func.h M rmi/on_chip.c M rmi/pic.h M rmi/xlr_machdep.c M rmi/ehcivar.h M rmi/board.c M rmi/clock.c M rmi/shared_structs_offsets.h M rmi/perfmon_utils.h M rmi/board.h M rmi/msgring_xls.c M rmi/intr_machdep.c
184 lines
5.1 KiB
C
184 lines
5.1 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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#ifndef PERFMON_H
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#define PERFMON_H
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#include <mips/rmi/perfmon_xlrconfig.h>
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/*
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* category events reported by the perfmon library
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*/
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enum event_category_t {
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PERF_CP0_COUNTER = 1, PERF_CP2_CREDITS, PERF_L2_COUNTER,
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PERF_SBC_COUNTER, PERF_SBC_CREDITS, PERF_GMAC0_COUNTER, PERF_GMAC1_COUNTER,
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PERF_GMAC2_COUNTER, PERF_GMAC_STAT_COM, PERF_GMAC_STAT_TX,
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PERF_GMAC_STAT_RX, PERF_DRAM_COUNTER, PERF_PARAMETER_CONF = 127};
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enum perf_param_t {
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PERF_CPU_SAMPLING_INTERVAL, PERF_SYS_SAMPLING_INTERVAL, PERF_CC_SAMPLE_RATE, PERF_CP0_FLAGS
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};
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#define CPO_EVENTS_TEMPLATE 0x06 /* enable kernel and user events */
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#define PERFMON_ACTIVE_MAGIC 0xc001
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#define PERFMON_ENABLED_MAGIC 0xb007
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#define PERFMON_INITIAL_GENERATION 0x0101
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#define PERFMON_SERVER_PORT 7007
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enum system_bridge_credits_t {
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PCIX_CREDITS, HT_CREDITS, GIO_CREDITS, OTHER_CREDITS
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};
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struct perf_config_data {
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uint16_t magic; /* monitor start when this is initialized */
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uint16_t generation; /* incremented when the config changes */
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uint16_t flags;
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uint16_t cc_sample_rate;/* rate at which credit counters are sampled
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* relative to sampling_rate */
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uint32_t sampling_rate; /* rate at which events are sampled */
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uint32_t cc_register_mask; /* credit counters registers to be
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* sampled */
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uint64_t events[NTHREADS]; /* events bitmap for each thread */
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};
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struct perf_sample {
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uint32_t counter;
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uint32_t timestamp;
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uint32_t sample_tag;
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uint32_t duration;
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};
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struct sample_q {
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int32_t head, tail;
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struct perf_sample samples[PERF_SAMPLE_BUFSZ];
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uint32_t overflows;
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};
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struct perf_area {
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struct perf_config_data perf_config;
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struct sample_q sample_fifo;
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};
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/*
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* We have a shared location to keep a global tick counter for all the
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* CPUS - TODO is this optimal? effect on cache?
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*/
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extern uint32_t *xlr_perfmon_timer_loc;
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#define PERFMON_TIMESTAMP_LOC (xlr_perfmon_timer_loc)
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static __inline__ uint32_t
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perfmon_timestamp_get(void)
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{
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return *PERFMON_TIMESTAMP_LOC;
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}
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static __inline__ void
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perfmon_timestamp_set(uint32_t val)
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{
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*PERFMON_TIMESTAMP_LOC = val;
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}
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static __inline__ void
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perfmon_timestamp_incr(int val)
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{
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(*PERFMON_TIMESTAMP_LOC) += val;
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}
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static __inline__ void
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send_sample_gts(uint32_t tag, uint32_t value, uint32_t td)
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{
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xlr_send_sample(tag, value, perfmon_timestamp_get(), td);
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}
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/*
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* Simple FIFO, one producer - one consumer - circlar queue - no locking
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*/
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static __inline__ void
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init_fifo(struct sample_q *q)
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{
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q->head = q->tail = 0;
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}
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static __inline__ void
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put_sample(struct sample_q *q, uint32_t sample_tag, uint32_t counter,
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uint32_t duration)
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{
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uint32_t timestamp = perfmon_timestamp_get();
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int new_tail = (q->tail + 1) % PERF_SAMPLE_BUFSZ;
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if (q->head == new_tail) {
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q->overflows++;
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return;
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}
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q->samples[new_tail].sample_tag = sample_tag;
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q->samples[new_tail].counter = counter;
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q->samples[new_tail].timestamp = timestamp;
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q->samples[new_tail].duration = duration;
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q->tail = new_tail;
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}
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static __inline__ int
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get_sample(struct sample_q *q, uint32_t * sample_tag, uint32_t * counter,
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uint32_t * timestamp, uint32_t * duration)
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{
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int head = q->head;
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if (head == q->tail)
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return 0;
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*sample_tag = q->samples[head].sample_tag;
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*counter = q->samples[head].counter;
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*timestamp = q->samples[head].timestamp;
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*duration = q->samples[head].duration;
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q->head = (head + 1) % PERF_SAMPLE_BUFSZ;
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return 1;
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}
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static __inline__ void
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clear_queue(struct sample_q *q)
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{
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q->head = q->tail;
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}
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void xlr_perfmon_init_cpu(void *);
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void xlr_perfmon_sampler(void *);
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void log_active_core(int core);
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int get_start_generation(void);
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void xlr_perfmon_clockhandler(void);
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extern int xlr_perfmon_started;
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#endif /* PERFMON_H */
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