ba74981e71
intr_{disable,restore} as well as providing an implemenation of
intr_{disable,restore}.
Reviewed by: jake, rwatson, jhb
875 lines
20 KiB
C
875 lines
20 KiB
C
/*
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* Copyright (c) KATO Takenori, 1997, 1998.
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*
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* All rights reserved. Unpublished rights reserved under the copyright
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* laws of Japan.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer as
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* the first lines of this file unmodified.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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void initializecpu(void);
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#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
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void enable_K5_wt_alloc(void);
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void enable_K6_wt_alloc(void);
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void enable_K6_2_wt_alloc(void);
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#endif
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#ifdef I486_CPU
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static void init_5x86(void);
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static void init_bluelightning(void);
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static void init_486dlc(void);
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static void init_cy486dx(void);
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#ifdef CPU_I486_ON_386
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static void init_i486_on_386(void);
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#endif
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static void init_6x86(void);
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#endif /* I486_CPU */
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#ifdef I686_CPU
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static void init_6x86MX(void);
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static void init_ppro(void);
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static void init_mendocino(void);
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#endif
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void enable_sse(void);
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int hw_instruction_sse = 0;
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SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
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&hw_instruction_sse, 0,
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"SIMD/MMX2 instructions available in CPU");
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/* Must *NOT* be BSS or locore will bzero these after setting them */
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int cpu = 0; /* Are we 386, 386sx, 486, etc? */
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u_int cpu_id = 0; /* Stepping ID */
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u_int cpu_feature = 0; /* Feature flags */
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u_int cpu_high = 0; /* Highest arg to CPUID */
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#ifdef CPU_ENABLE_SSE
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u_int cpu_fxsr = 0; /* SSE enabled */
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#endif
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char cpu_vendor[20] = ""; /* CPU Origin code */
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#ifdef I486_CPU
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/*
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* IBM Blue Lightning
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*/
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static void
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init_bluelightning(void)
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{
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u_long eflags;
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#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
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need_post_dma_flush = 1;
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#endif
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eflags = read_eflags();
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disable_intr();
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load_cr0(rcr0() | CR0_CD | CR0_NW);
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invd();
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#ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
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wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
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#else
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wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
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#endif
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/* Enables 13MB and 0-640KB cache. */
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wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
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#ifdef CPU_BLUELIGHTNING_3X
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wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
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#else
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wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
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#endif
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/* Enable caching in CR0. */
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load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
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invd();
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write_eflags(eflags);
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}
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/*
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* Cyrix 486SLC/DLC/SR/DR series
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*/
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static void
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init_486dlc(void)
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{
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u_long eflags;
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u_char ccr0;
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eflags = read_eflags();
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disable_intr();
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invd();
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ccr0 = read_cyrix_reg(CCR0);
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#ifndef CYRIX_CACHE_WORKS
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ccr0 |= CCR0_NC1 | CCR0_BARB;
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write_cyrix_reg(CCR0, ccr0);
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invd();
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#else
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ccr0 &= ~CCR0_NC0;
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#ifndef CYRIX_CACHE_REALLY_WORKS
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ccr0 |= CCR0_NC1 | CCR0_BARB;
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#else
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ccr0 |= CCR0_NC1;
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#endif
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#ifdef CPU_DIRECT_MAPPED_CACHE
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ccr0 |= CCR0_CO; /* Direct mapped mode. */
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#endif
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write_cyrix_reg(CCR0, ccr0);
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/* Clear non-cacheable region. */
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write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
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write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
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write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
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write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
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write_cyrix_reg(0, 0); /* dummy write */
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/* Enable caching in CR0. */
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load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
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invd();
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#endif /* !CYRIX_CACHE_WORKS */
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write_eflags(eflags);
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}
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/*
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* Cyrix 486S/DX series
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*/
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static void
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init_cy486dx(void)
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{
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u_long eflags;
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u_char ccr2;
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eflags = read_eflags();
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disable_intr();
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invd();
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ccr2 = read_cyrix_reg(CCR2);
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#ifdef CPU_SUSP_HLT
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ccr2 |= CCR2_SUSP_HLT;
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#endif
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#ifdef PC98
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/* Enables WB cache interface pin and Lock NW bit in CR0. */
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ccr2 |= CCR2_WB | CCR2_LOCK_NW;
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/* Unlock NW bit in CR0. */
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write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
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load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
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#endif
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write_cyrix_reg(CCR2, ccr2);
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write_eflags(eflags);
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}
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/*
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* Cyrix 5x86
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*/
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static void
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init_5x86(void)
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{
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u_long eflags;
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u_char ccr2, ccr3, ccr4, pcr0;
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eflags = read_eflags();
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disable_intr();
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load_cr0(rcr0() | CR0_CD | CR0_NW);
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wbinvd();
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(void)read_cyrix_reg(CCR3); /* dummy */
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/* Initialize CCR2. */
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ccr2 = read_cyrix_reg(CCR2);
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ccr2 |= CCR2_WB;
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#ifdef CPU_SUSP_HLT
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ccr2 |= CCR2_SUSP_HLT;
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#else
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ccr2 &= ~CCR2_SUSP_HLT;
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#endif
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ccr2 |= CCR2_WT1;
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write_cyrix_reg(CCR2, ccr2);
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/* Initialize CCR4. */
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ccr3 = read_cyrix_reg(CCR3);
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write_cyrix_reg(CCR3, CCR3_MAPEN0);
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ccr4 = read_cyrix_reg(CCR4);
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ccr4 |= CCR4_DTE;
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ccr4 |= CCR4_MEM;
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#ifdef CPU_FASTER_5X86_FPU
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ccr4 |= CCR4_FASTFPE;
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#else
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ccr4 &= ~CCR4_FASTFPE;
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#endif
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ccr4 &= ~CCR4_IOMASK;
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/********************************************************************
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* WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
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* should be 0 for errata fix.
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********************************************************************/
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#ifdef CPU_IORT
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ccr4 |= CPU_IORT & CCR4_IOMASK;
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#endif
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write_cyrix_reg(CCR4, ccr4);
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/* Initialize PCR0. */
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/****************************************************************
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* WARNING: RSTK_EN and LOOP_EN could make your system unstable.
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* BTB_EN might make your system unstable.
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****************************************************************/
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pcr0 = read_cyrix_reg(PCR0);
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#ifdef CPU_RSTK_EN
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pcr0 |= PCR0_RSTK;
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#else
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pcr0 &= ~PCR0_RSTK;
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#endif
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#ifdef CPU_BTB_EN
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pcr0 |= PCR0_BTB;
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#else
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pcr0 &= ~PCR0_BTB;
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#endif
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#ifdef CPU_LOOP_EN
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pcr0 |= PCR0_LOOP;
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#else
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pcr0 &= ~PCR0_LOOP;
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#endif
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/****************************************************************
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* WARNING: if you use a memory mapped I/O device, don't use
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* DISABLE_5X86_LSSER option, which may reorder memory mapped
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* I/O access.
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* IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
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****************************************************************/
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#ifdef CPU_DISABLE_5X86_LSSER
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pcr0 &= ~PCR0_LSSER;
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#else
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pcr0 |= PCR0_LSSER;
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#endif
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write_cyrix_reg(PCR0, pcr0);
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/* Restore CCR3. */
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write_cyrix_reg(CCR3, ccr3);
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(void)read_cyrix_reg(0x80); /* dummy */
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/* Unlock NW bit in CR0. */
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
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load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
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/* Lock NW bit in CR0. */
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
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write_eflags(eflags);
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}
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#ifdef CPU_I486_ON_386
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/*
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* There are i486 based upgrade products for i386 machines.
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* In this case, BIOS doesn't enables CPU cache.
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*/
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void
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init_i486_on_386(void)
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{
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u_long eflags;
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#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
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need_post_dma_flush = 1;
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#endif
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eflags = read_eflags();
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disable_intr();
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load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
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write_eflags(eflags);
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}
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#endif
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/*
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* Cyrix 6x86
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*
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* XXX - What should I do here? Please let me know.
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*/
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static void
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init_6x86(void)
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{
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u_long eflags;
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u_char ccr3, ccr4;
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eflags = read_eflags();
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disable_intr();
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load_cr0(rcr0() | CR0_CD | CR0_NW);
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wbinvd();
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/* Initialize CCR0. */
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
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/* Initialize CCR1. */
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#ifdef CPU_CYRIX_NO_LOCK
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write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
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#else
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write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
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#endif
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/* Initialize CCR2. */
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#ifdef CPU_SUSP_HLT
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
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#else
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
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#endif
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ccr3 = read_cyrix_reg(CCR3);
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write_cyrix_reg(CCR3, CCR3_MAPEN0);
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/* Initialize CCR4. */
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ccr4 = read_cyrix_reg(CCR4);
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ccr4 |= CCR4_DTE;
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ccr4 &= ~CCR4_IOMASK;
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#ifdef CPU_IORT
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write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
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#else
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write_cyrix_reg(CCR4, ccr4 | 7);
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#endif
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/* Initialize CCR5. */
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#ifdef CPU_WT_ALLOC
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write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
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#endif
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/* Restore CCR3. */
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write_cyrix_reg(CCR3, ccr3);
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/* Unlock NW bit in CR0. */
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
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/*
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* Earlier revision of the 6x86 CPU could crash the system if
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* L1 cache is in write-back mode.
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*/
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if ((cyrix_did & 0xff00) > 0x1600)
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load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
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else {
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/* Revision 2.6 and lower. */
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#ifdef CYRIX_CACHE_REALLY_WORKS
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load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
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#else
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load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
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#endif
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}
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/* Lock NW bit in CR0. */
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
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write_eflags(eflags);
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}
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#endif /* I486_CPU */
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#ifdef I686_CPU
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/*
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* Cyrix 6x86MX (code-named M2)
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*
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* XXX - What should I do here? Please let me know.
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*/
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static void
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init_6x86MX(void)
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{
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u_long eflags;
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u_char ccr3, ccr4;
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eflags = read_eflags();
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disable_intr();
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load_cr0(rcr0() | CR0_CD | CR0_NW);
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wbinvd();
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/* Initialize CCR0. */
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
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/* Initialize CCR1. */
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#ifdef CPU_CYRIX_NO_LOCK
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write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
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#else
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write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
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#endif
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/* Initialize CCR2. */
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#ifdef CPU_SUSP_HLT
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
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#else
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
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#endif
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ccr3 = read_cyrix_reg(CCR3);
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write_cyrix_reg(CCR3, CCR3_MAPEN0);
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/* Initialize CCR4. */
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ccr4 = read_cyrix_reg(CCR4);
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ccr4 &= ~CCR4_IOMASK;
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#ifdef CPU_IORT
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write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
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#else
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write_cyrix_reg(CCR4, ccr4 | 7);
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#endif
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/* Initialize CCR5. */
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#ifdef CPU_WT_ALLOC
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write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
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#endif
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/* Restore CCR3. */
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write_cyrix_reg(CCR3, ccr3);
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/* Unlock NW bit in CR0. */
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
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load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
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/* Lock NW bit in CR0. */
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
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write_eflags(eflags);
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}
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static void
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init_ppro(void)
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{
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#ifndef SMP
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u_int64_t apicbase;
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/*
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* Local APIC should be diabled in UP kernel.
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*/
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apicbase = rdmsr(0x1b);
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apicbase &= ~0x800LL;
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wrmsr(0x1b, apicbase);
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#endif
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}
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/*
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* Initialize BBL_CR_CTL3 (Control register 3: used to configure the
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* L2 cache).
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*/
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void
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init_mendocino(void)
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{
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#ifdef CPU_PPRO2CELERON
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u_long eflags;
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u_int64_t bbl_cr_ctl3;
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eflags = read_eflags();
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disable_intr();
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load_cr0(rcr0() | CR0_CD | CR0_NW);
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wbinvd();
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bbl_cr_ctl3 = rdmsr(0x11e);
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/* If the L2 cache is configured, do nothing. */
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|
if (!(bbl_cr_ctl3 & 1)) {
|
|
bbl_cr_ctl3 = 0x134052bLL;
|
|
|
|
/* Set L2 Cache Latency (Default: 5). */
|
|
#ifdef CPU_CELERON_L2_LATENCY
|
|
#if CPU_L2_LATENCY > 15
|
|
#error invalid CPU_L2_LATENCY.
|
|
#endif
|
|
bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
|
|
#else
|
|
bbl_cr_ctl3 |= 5 << 1;
|
|
#endif
|
|
wrmsr(0x11e, bbl_cr_ctl3);
|
|
}
|
|
|
|
load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
|
|
write_eflags(eflags);
|
|
#endif /* CPU_PPRO2CELERON */
|
|
}
|
|
|
|
#endif /* I686_CPU */
|
|
|
|
/*
|
|
* Initialize CR4 (Control register 4) to enable SSE instructions.
|
|
*/
|
|
void
|
|
enable_sse(void)
|
|
{
|
|
#if defined(CPU_ENABLE_SSE)
|
|
if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
|
|
load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
|
|
cpu_fxsr = hw_instruction_sse = 1;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
initializecpu(void)
|
|
{
|
|
|
|
switch (cpu) {
|
|
#ifdef I486_CPU
|
|
case CPU_BLUE:
|
|
init_bluelightning();
|
|
break;
|
|
case CPU_486DLC:
|
|
init_486dlc();
|
|
break;
|
|
case CPU_CY486DX:
|
|
init_cy486dx();
|
|
break;
|
|
case CPU_M1SC:
|
|
init_5x86();
|
|
break;
|
|
#ifdef CPU_I486_ON_386
|
|
case CPU_486:
|
|
init_i486_on_386();
|
|
break;
|
|
#endif
|
|
case CPU_M1:
|
|
init_6x86();
|
|
break;
|
|
#endif /* I486_CPU */
|
|
#ifdef I686_CPU
|
|
case CPU_M2:
|
|
init_6x86MX();
|
|
break;
|
|
case CPU_686:
|
|
if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
|
|
switch (cpu_id & 0xff0) {
|
|
case 0x610:
|
|
init_ppro();
|
|
break;
|
|
case 0x660:
|
|
init_mendocino();
|
|
break;
|
|
}
|
|
} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
|
|
#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
|
|
/*
|
|
* Sometimes the BIOS doesn't enable SSE instructions.
|
|
* According to AMD document 20734, the mobile
|
|
* Duron, the (mobile) Athlon 4 and the Athlon MP
|
|
* support SSE. These correspond to cpu_id 0x66X
|
|
* or 0x67X.
|
|
*/
|
|
if ((cpu_feature & CPUID_XMM) == 0 &&
|
|
((cpu_id & ~0xf) == 0x660 ||
|
|
(cpu_id & ~0xf) == 0x670)) {
|
|
u_int regs[4];
|
|
wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
|
|
do_cpuid(1, regs);
|
|
cpu_feature = regs[3];
|
|
}
|
|
#endif
|
|
}
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
enable_sse();
|
|
|
|
#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
|
|
/*
|
|
* OS should flush L1 cache by itself because no PC-98 supports
|
|
* non-Intel CPUs. Use wbinvd instruction before DMA transfer
|
|
* when need_pre_dma_flush = 1, use invd instruction after DMA
|
|
* transfer when need_post_dma_flush = 1. If your CPU upgrade
|
|
* product supports hardware cache control, you can add the
|
|
* CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
|
|
* This option eliminates unneeded cache flush instruction(s).
|
|
*/
|
|
if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
|
|
switch (cpu) {
|
|
#ifdef I486_CPU
|
|
case CPU_486DLC:
|
|
need_post_dma_flush = 1;
|
|
break;
|
|
case CPU_M1SC:
|
|
need_pre_dma_flush = 1;
|
|
break;
|
|
case CPU_CY486DX:
|
|
need_pre_dma_flush = 1;
|
|
#ifdef CPU_I486_ON_386
|
|
need_post_dma_flush = 1;
|
|
#endif
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
|
|
switch (cpu_id & 0xFF0) {
|
|
case 0x470: /* Enhanced Am486DX2 WB */
|
|
case 0x490: /* Enhanced Am486DX4 WB */
|
|
case 0x4F0: /* Am5x86 WB */
|
|
need_pre_dma_flush = 1;
|
|
break;
|
|
}
|
|
} else if (strcmp(cpu_vendor, "IBM") == 0) {
|
|
need_post_dma_flush = 1;
|
|
} else {
|
|
#ifdef CPU_I486_ON_386
|
|
need_pre_dma_flush = 1;
|
|
#endif
|
|
}
|
|
#endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
|
|
}
|
|
|
|
#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
|
|
/*
|
|
* Enable write allocate feature of AMD processors.
|
|
* Following two functions require the Maxmem variable being set.
|
|
*/
|
|
void
|
|
enable_K5_wt_alloc(void)
|
|
{
|
|
u_int64_t msr;
|
|
register_t savecrit;
|
|
|
|
/*
|
|
* Write allocate is supported only on models 1, 2, and 3, with
|
|
* a stepping of 4 or greater.
|
|
*/
|
|
if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
|
|
savecrit = intr_disable();
|
|
msr = rdmsr(0x83); /* HWCR */
|
|
wrmsr(0x83, msr & !(0x10));
|
|
|
|
/*
|
|
* We have to tell the chip where the top of memory is,
|
|
* since video cards could have frame bufferes there,
|
|
* memory-mapped I/O could be there, etc.
|
|
*/
|
|
if(Maxmem > 0)
|
|
msr = Maxmem / 16;
|
|
else
|
|
msr = 0;
|
|
msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
|
|
#ifdef PC98
|
|
if (!(inb(0x43b) & 4)) {
|
|
wrmsr(0x86, 0x0ff00f0);
|
|
msr |= AMD_WT_ALLOC_PRE;
|
|
}
|
|
#else
|
|
/*
|
|
* There is no way to know wheter 15-16M hole exists or not.
|
|
* Therefore, we disable write allocate for this range.
|
|
*/
|
|
wrmsr(0x86, 0x0ff00f0);
|
|
msr |= AMD_WT_ALLOC_PRE;
|
|
#endif
|
|
wrmsr(0x85, msr);
|
|
|
|
msr=rdmsr(0x83);
|
|
wrmsr(0x83, msr|0x10); /* enable write allocate */
|
|
intr_restore(savecrit);
|
|
}
|
|
}
|
|
|
|
void
|
|
enable_K6_wt_alloc(void)
|
|
{
|
|
quad_t size;
|
|
u_int64_t whcr;
|
|
u_long eflags;
|
|
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
wbinvd();
|
|
|
|
#ifdef CPU_DISABLE_CACHE
|
|
/*
|
|
* Certain K6-2 box becomes unstable when write allocation is
|
|
* enabled.
|
|
*/
|
|
/*
|
|
* The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
|
|
* but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
|
|
* All other bits in TR12 have no effect on the processer's operation.
|
|
* The I/O Trap Restart function (bit 9 of TR12) is always enabled
|
|
* on the AMD-K6.
|
|
*/
|
|
wrmsr(0x0000000e, (u_int64_t)0x0008);
|
|
#endif
|
|
/* Don't assume that memory size is aligned with 4M. */
|
|
if (Maxmem > 0)
|
|
size = ((Maxmem >> 8) + 3) >> 2;
|
|
else
|
|
size = 0;
|
|
|
|
/* Limit is 508M bytes. */
|
|
if (size > 0x7f)
|
|
size = 0x7f;
|
|
whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
|
|
|
|
#if defined(PC98) || defined(NO_MEMORY_HOLE)
|
|
if (whcr & (0x7fLL << 1)) {
|
|
#ifdef PC98
|
|
/*
|
|
* If bit 2 of port 0x43b is 0, disable wrte allocate for the
|
|
* 15-16M range.
|
|
*/
|
|
if (!(inb(0x43b) & 4))
|
|
whcr &= ~0x0001LL;
|
|
else
|
|
#endif
|
|
whcr |= 0x0001LL;
|
|
}
|
|
#else
|
|
/*
|
|
* There is no way to know wheter 15-16M hole exists or not.
|
|
* Therefore, we disable write allocate for this range.
|
|
*/
|
|
whcr &= ~0x0001LL;
|
|
#endif
|
|
wrmsr(0x0c0000082, whcr);
|
|
|
|
write_eflags(eflags);
|
|
}
|
|
|
|
void
|
|
enable_K6_2_wt_alloc(void)
|
|
{
|
|
quad_t size;
|
|
u_int64_t whcr;
|
|
u_long eflags;
|
|
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
wbinvd();
|
|
|
|
#ifdef CPU_DISABLE_CACHE
|
|
/*
|
|
* Certain K6-2 box becomes unstable when write allocation is
|
|
* enabled.
|
|
*/
|
|
/*
|
|
* The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
|
|
* but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
|
|
* All other bits in TR12 have no effect on the processer's operation.
|
|
* The I/O Trap Restart function (bit 9 of TR12) is always enabled
|
|
* on the AMD-K6.
|
|
*/
|
|
wrmsr(0x0000000e, (u_int64_t)0x0008);
|
|
#endif
|
|
/* Don't assume that memory size is aligned with 4M. */
|
|
if (Maxmem > 0)
|
|
size = ((Maxmem >> 8) + 3) >> 2;
|
|
else
|
|
size = 0;
|
|
|
|
/* Limit is 4092M bytes. */
|
|
if (size > 0x3fff)
|
|
size = 0x3ff;
|
|
whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
|
|
|
|
#if defined(PC98) || defined(NO_MEMORY_HOLE)
|
|
if (whcr & (0x3ffLL << 22)) {
|
|
#ifdef PC98
|
|
/*
|
|
* If bit 2 of port 0x43b is 0, disable wrte allocate for the
|
|
* 15-16M range.
|
|
*/
|
|
if (!(inb(0x43b) & 4))
|
|
whcr &= ~(1LL << 16);
|
|
else
|
|
#endif
|
|
whcr |= 1LL << 16;
|
|
}
|
|
#else
|
|
/*
|
|
* There is no way to know wheter 15-16M hole exists or not.
|
|
* Therefore, we disable write allocate for this range.
|
|
*/
|
|
whcr &= ~(1LL << 16);
|
|
#endif
|
|
wrmsr(0x0c0000082, whcr);
|
|
|
|
write_eflags(eflags);
|
|
}
|
|
#endif /* I585_CPU && CPU_WT_ALLOC */
|
|
|
|
#include "opt_ddb.h"
|
|
#ifdef DDB
|
|
#include <ddb/ddb.h>
|
|
|
|
DB_SHOW_COMMAND(cyrixreg, cyrixreg)
|
|
{
|
|
u_long eflags;
|
|
u_int cr0;
|
|
u_char ccr1, ccr2, ccr3;
|
|
u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
|
|
|
|
cr0 = rcr0();
|
|
if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
|
|
|
|
if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
|
|
ccr0 = read_cyrix_reg(CCR0);
|
|
}
|
|
ccr1 = read_cyrix_reg(CCR1);
|
|
ccr2 = read_cyrix_reg(CCR2);
|
|
ccr3 = read_cyrix_reg(CCR3);
|
|
if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
|
|
write_cyrix_reg(CCR3, CCR3_MAPEN0);
|
|
ccr4 = read_cyrix_reg(CCR4);
|
|
if ((cpu == CPU_M1) || (cpu == CPU_M2))
|
|
ccr5 = read_cyrix_reg(CCR5);
|
|
else
|
|
pcr0 = read_cyrix_reg(PCR0);
|
|
write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
|
|
}
|
|
write_eflags(eflags);
|
|
|
|
if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
|
|
printf("CCR0=%x, ", (u_int)ccr0);
|
|
|
|
printf("CCR1=%x, CCR2=%x, CCR3=%x",
|
|
(u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
|
|
if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
|
|
printf(", CCR4=%x, ", (u_int)ccr4);
|
|
if (cpu == CPU_M1SC)
|
|
printf("PCR0=%x\n", pcr0);
|
|
else
|
|
printf("CCR5=%x\n", ccr5);
|
|
}
|
|
}
|
|
printf("CR0=%x\n", cr0);
|
|
}
|
|
#endif /* DDB */
|