68c30b183a
Machine privilege level was specially designed to use in vendor's firmware or bootloader. We have implemented operation in machine mode in FreeBSD as part of understanding RISC-V ISA, but it is time to remove it. We now use BBL (Berkeley Boot Loader) -- standard RISC-V firmware, which provides operation in machine mode for us. We now use standard SBI calls to machine mode, instead of handmade 'syscalls'. o Remove HTIF bus. HTIF bus is now legacy and no longer exists in RISC-V specification. HTIF code still exists in Spike simulator, but BBL do not provide raw interface to it. Memory disk is only choice for now to have multiuser booted in Spike, until Spike has implemented more devices (e.g. Virtio, etc). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
/*-
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* Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#ifdef _KERNEL
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#include <machine/riscvreg.h>
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static __inline void
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breakpoint(void)
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{
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__asm("ebreak");
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}
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static __inline register_t
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intr_disable(void)
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{
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uint64_t ret;
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__asm __volatile(
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"csrrci %0, sstatus, %1"
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: "=&r" (ret) : "i" (SSTATUS_SIE)
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);
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return (ret & (SSTATUS_SIE));
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}
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static __inline void
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intr_restore(register_t s)
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{
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__asm __volatile(
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"csrs sstatus, %0"
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:: "r" (s)
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);
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}
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static __inline void
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intr_enable(void)
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{
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__asm __volatile(
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"csrsi sstatus, %0"
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:: "i" (SSTATUS_SIE)
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);
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}
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#define cpu_nullop() riscv_nullop()
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#define cpufunc_nullop() riscv_nullop()
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#define cpu_setttb(a) riscv_setttb(a)
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#define cpu_tlb_flushID() riscv_tlb_flushID()
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#define cpu_tlb_flushID_SE(e) riscv_tlb_flushID_SE(e)
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#define cpu_dcache_wbinv_range(a, s) riscv_dcache_wbinv_range((a), (s))
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#define cpu_dcache_inv_range(a, s) riscv_dcache_inv_range((a), (s))
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#define cpu_dcache_wb_range(a, s) riscv_dcache_wb_range((a), (s))
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#define cpu_idcache_wbinv_range(a, s) riscv_idcache_wbinv_range((a), (s))
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#define cpu_icache_sync_range(a, s) riscv_icache_sync_range((a), (s))
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void riscv_nullop(void);
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void riscv_setttb(vm_offset_t);
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void riscv_tlb_flushID(void);
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void riscv_tlb_flushID_SE(vm_offset_t);
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void riscv_icache_sync_range(vm_offset_t, vm_size_t);
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void riscv_idcache_wbinv_range(vm_offset_t, vm_size_t);
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void riscv_dcache_wbinv_range(vm_offset_t, vm_size_t);
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void riscv_dcache_inv_range(vm_offset_t, vm_size_t);
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void riscv_dcache_wb_range(vm_offset_t, vm_size_t);
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#endif /* _KERNEL */
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#endif /* _MACHINE_CPUFUNC_H_ */
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