264 lines
9.1 KiB
C
264 lines
9.1 KiB
C
/*-
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* Copyright (C) 2001 Eduardo Horvath.
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* Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
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* from: FreeBSD: if_gemvar.h 177560 2008-03-24 17:23:53Z marius
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*
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* $FreeBSD$
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*/
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#ifndef _IF_CASVAR_H
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#define _IF_CASVAR_H
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/*
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* The page size is configurable, but needs to be at least 8k (the
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* default) in order to also support jumbo buffers.
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*/
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#define CAS_PAGE_SIZE 8192
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/*
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* Transmit descriptor ring size - this is arbitrary, but allocate
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* enough descriptors for 64 pending transmissions and 16 segments
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* per packet. This limit is not actually enforced (packets with
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* more segments can be sent, depending on the busdma backend); it
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* is however used as an estimate for the TX window size.
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*/
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#define CAS_NTXSEGS 16
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#define CAS_TXQUEUELEN 64
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#define CAS_NTXDESC (CAS_TXQUEUELEN * CAS_NTXSEGS)
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#define CAS_MAXTXFREE (CAS_NTXDESC - 1)
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#define CAS_NTXDESC_MASK (CAS_NTXDESC - 1)
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#define CAS_NEXTTX(x) ((x + 1) & CAS_NTXDESC_MASK)
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/*
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* Receive completion ring size - we have one completion per
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* incoming packet (though the opposite isn't necessarily true),
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* so this logic is a little simpler.
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*/
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#define CAS_NRXCOMP 4096
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#define CAS_NRXCOMP_MASK (CAS_NRXCOMP - 1)
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#define CAS_NEXTRXCOMP(x) ((x + 1) & CAS_NRXCOMP_MASK)
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/*
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* Receive descriptor ring sizes - for Cassini+ and Saturn both
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* rings must be at least initialized.
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*/
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#define CAS_NRXDESC 1024
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#define CAS_NRXDESC_MASK (CAS_NRXDESC - 1)
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#define CAS_NEXTRXDESC(x) ((x + 1) & CAS_NRXDESC_MASK)
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#define CAS_NRXDESC2 32
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#define CAS_NRXDESC2_MASK (CAS_NRXDESC2 - 1)
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#define CAS_NEXTRXDESC2(x) ((x + 1) & CAS_NRXDESC2_MASK)
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/*
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* How many ticks to wait until to retry on a RX descriptor that is
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* still owned by the hardware.
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*/
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#define CAS_RXOWN_TICKS (hz / 50)
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/*
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* Control structures are DMA'd to the chip. We allocate them
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* in a single clump that maps to a single DMA segment to make
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* several things easier.
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*/
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struct cas_control_data {
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struct cas_desc ccd_txdescs[CAS_NTXDESC]; /* TX descriptors */
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struct cas_rx_comp ccd_rxcomps[CAS_NRXCOMP]; /* RX completions */
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struct cas_desc ccd_rxdescs[CAS_NRXDESC]; /* RX descriptors */
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struct cas_desc ccd_rxdescs2[CAS_NRXDESC2]; /* RX descriptors 2 */
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};
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#define CAS_CDOFF(x) offsetof(struct cas_control_data, x)
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#define CAS_CDTXDOFF(x) CAS_CDOFF(ccd_txdescs[(x)])
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#define CAS_CDRXCOFF(x) CAS_CDOFF(ccd_rxcomps[(x)])
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#define CAS_CDRXDOFF(x) CAS_CDOFF(ccd_rxdescs[(x)])
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#define CAS_CDRXD2OFF(x) CAS_CDOFF(ccd_rxdescs2[(x)])
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/*
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* software state for transmit job mbufs (may be elements of mbuf chains)
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*/
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struct cas_txsoft {
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struct mbuf *txs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t txs_dmamap; /* our DMA map */
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u_int txs_firstdesc; /* first descriptor in packet */
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u_int txs_lastdesc; /* last descriptor in packet */
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u_int txs_ndescs; /* number of descriptors */
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STAILQ_ENTRY(cas_txsoft) txs_q;
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};
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STAILQ_HEAD(cas_txsq, cas_txsoft);
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/*
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* software state for receive descriptors
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*/
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struct cas_rxdsoft {
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void *rxds_buf; /* receive buffer */
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bus_dmamap_t rxds_dmamap; /* our DMA map */
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bus_addr_t rxds_paddr; /* physical address of the segment */
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#if __FreeBSD_version < 800016
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struct cas_softc *rxds_sc; /* softc pointer */
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u_int rxds_idx; /* our index */
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#endif
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u_int rxds_refcount; /* hardware + mbuf references */
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};
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/*
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* software state per device
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*/
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struct cas_softc {
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struct ifnet *sc_ifp;
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struct mtx sc_mtx;
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device_t sc_miibus;
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struct mii_data *sc_mii; /* MII media control */
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device_t sc_dev; /* generic device information */
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u_char sc_enaddr[ETHER_ADDR_LEN];
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struct callout sc_tick_ch; /* tick callout */
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struct callout sc_rx_ch; /* delayed RX callout */
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struct task sc_intr_task;
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struct task sc_tx_task;
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struct taskqueue *sc_tq;
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u_int sc_wdog_timer; /* watchdog timer */
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void *sc_ih;
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struct resource *sc_res[2];
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#define CAS_RES_INTR 0
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#define CAS_RES_MEM 1
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bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */
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bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */
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bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */
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bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */
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bus_dmamap_t sc_dmamap; /* bus DMA handle */
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u_int sc_variant;
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#define CAS_UNKNOWN 0 /* don't know */
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#define CAS_CAS 1 /* Sun Cassini */
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#define CAS_CASPLUS 2 /* Sun Cassini+ */
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#define CAS_SATURN 3 /* National Semiconductor Saturn */
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u_int sc_flags;
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#define CAS_INITED (1 << 0) /* reset persistent regs init'ed */
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#define CAS_NO_CSUM (1 << 1) /* don't use hardware checksumming */
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#define CAS_LINK (1 << 2) /* link is up */
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#define CAS_REG_PLUS (1 << 3) /* has Cassini+ registers */
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#define CAS_SERDES (1 << 4) /* use the SERDES */
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#define CAS_TABORT (1 << 5) /* has target abort issues */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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bus_addr_t sc_cddma;
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/*
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* software state for transmit and receive descriptors
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*/
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struct cas_txsoft sc_txsoft[CAS_TXQUEUELEN];
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struct cas_rxdsoft sc_rxdsoft[CAS_NRXDESC];
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/*
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* control data structures
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*/
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struct cas_control_data *sc_control_data;
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#define sc_txdescs sc_control_data->ccd_txdescs
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#define sc_rxcomps sc_control_data->ccd_rxcomps
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#define sc_rxdescs sc_control_data->ccd_rxdescs
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#define sc_rxdescs2 sc_control_data->ccd_rxdescs2
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u_int sc_txfree; /* number of free TX descriptors */
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u_int sc_txnext; /* next ready TX descriptor */
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u_int sc_txwin; /* TX desc. since last TX intr. */
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struct cas_txsq sc_txfreeq; /* free software TX descriptors */
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struct cas_txsq sc_txdirtyq; /* dirty software TX descriptors */
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u_int sc_rxcptr; /* next ready RX completion */
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u_int sc_rxdptr; /* next ready RX descriptor */
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uint32_t sc_mac_rxcfg; /* RX MAC conf. % CAS_MAC_RX_CONF_EN */
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int sc_ifflags;
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};
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#define CAS_BARRIER(sc, offs, len, flags) \
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bus_barrier((sc)->sc_res[CAS_RES_MEM], (offs), (len), (flags))
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#define CAS_READ_N(n, sc, offs) \
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bus_read_ ## n((sc)->sc_res[CAS_RES_MEM], (offs))
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#define CAS_READ_1(sc, offs) CAS_READ_N(1, (sc), (offs))
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#define CAS_READ_2(sc, offs) CAS_READ_N(2, (sc), (offs))
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#define CAS_READ_4(sc, offs) CAS_READ_N(4, (sc), (offs))
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#define CAS_WRITE_N(n, sc, offs, v) \
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bus_write_ ## n((sc)->sc_res[CAS_RES_MEM], (offs), (v))
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#define CAS_WRITE_1(sc, offs, v) CAS_WRITE_N(1, (sc), (offs), (v))
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#define CAS_WRITE_2(sc, offs, v) CAS_WRITE_N(2, (sc), (offs), (v))
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#define CAS_WRITE_4(sc, offs, v) CAS_WRITE_N(4, (sc), (offs), (v))
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#define CAS_CDTXDADDR(sc, x) ((sc)->sc_cddma + CAS_CDTXDOFF((x)))
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#define CAS_CDRXCADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXCOFF((x)))
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#define CAS_CDRXDADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXDOFF((x)))
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#define CAS_CDRXD2ADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXD2OFF((x)))
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#define CAS_CDSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops));
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#define __CAS_UPDATE_RXDESC(rxd, rxds, s) \
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do { \
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\
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refcount_init(&(rxds)->rxds_refcount, 1); \
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(rxd)->cd_buf_ptr = htole64((rxds)->rxds_paddr); \
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KASSERT((s) < CAS_RD_BUF_INDEX_MASK >> CAS_RD_BUF_INDEX_SHFT, \
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("%s: RX buffer index too large!", __func__)); \
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(rxd)->cd_flags = \
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htole64((uint64_t)((s) << CAS_RD_BUF_INDEX_SHFT)); \
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} while (0)
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#define CAS_UPDATE_RXDESC(sc, d, s) \
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__CAS_UPDATE_RXDESC(&(sc)->sc_rxdescs[(d)], \
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&(sc)->sc_rxdsoft[(s)], (s))
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#if __FreeBSD_version < 800016
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#define CAS_INIT_RXDESC(sc, d, s) \
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do { \
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struct cas_rxdsoft *__rxds = &(sc)->sc_rxdsoft[(s)]; \
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\
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__rxds->rxds_sc = (sc); \
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__rxds->rxds_idx = (s); \
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__CAS_UPDATE_RXDESC(&(sc)->sc_rxdescs[(d)], __rxds, (s)); \
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} while (0)
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#else
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#define CAS_INIT_RXDESC(sc, d, s) CAS_UPDATE_RXDESC(sc, d, s)
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#endif
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#define CAS_LOCK_INIT(_sc, _name) \
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mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
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#define CAS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define CAS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define CAS_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
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#define CAS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define CAS_LOCK_OWNED(_sc) mtx_owned(&(_sc)->sc_mtx)
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#endif
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