46b29ff94a
PR: 118739 Submitted by: Dan Lukes <dan@obluda.cz> (earlier version) Reviewed by: jhb Approved by: sbruno (mentor) MFC after: 1 week
348 lines
9.0 KiB
C
348 lines
9.0 KiB
C
/*-
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* Copyright (c) 2005 Nate Lawson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Throttle clock frequency by using the thermal control circuit. This
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* operates independently of SpeedStep and ACPI throttling and is supported
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* on Pentium 4 and later models (feature TM).
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*
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* Reference: Intel Developer's manual v.3 #245472-012
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*
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* The original version of this driver was written by Ted Unangst for
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* OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson
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* for use with the cpufreq framework.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#include "cpufreq_if.h"
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#include <contrib/dev/acpica/include/acpi.h>
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#include <dev/acpica/acpivar.h>
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#include "acpi_if.h"
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struct p4tcc_softc {
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device_t dev;
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int set_count;
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int lowest_val;
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int auto_mode;
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};
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#define TCC_NUM_SETTINGS 8
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#define TCC_ENABLE_ONDEMAND (1<<4)
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#define TCC_REG_OFFSET 1
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#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS)
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static int p4tcc_features(driver_t *driver, u_int *features);
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static void p4tcc_identify(driver_t *driver, device_t parent);
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static int p4tcc_probe(device_t dev);
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static int p4tcc_attach(device_t dev);
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static int p4tcc_detach(device_t dev);
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static int p4tcc_settings(device_t dev, struct cf_setting *sets,
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int *count);
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static int p4tcc_set(device_t dev, const struct cf_setting *set);
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static int p4tcc_get(device_t dev, struct cf_setting *set);
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static int p4tcc_type(device_t dev, int *type);
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static device_method_t p4tcc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, p4tcc_identify),
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DEVMETHOD(device_probe, p4tcc_probe),
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DEVMETHOD(device_attach, p4tcc_attach),
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DEVMETHOD(device_detach, p4tcc_detach),
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/* cpufreq interface */
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DEVMETHOD(cpufreq_drv_set, p4tcc_set),
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DEVMETHOD(cpufreq_drv_get, p4tcc_get),
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DEVMETHOD(cpufreq_drv_type, p4tcc_type),
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DEVMETHOD(cpufreq_drv_settings, p4tcc_settings),
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/* ACPI interface */
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DEVMETHOD(acpi_get_features, p4tcc_features),
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{0, 0}
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};
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static driver_t p4tcc_driver = {
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"p4tcc",
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p4tcc_methods,
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sizeof(struct p4tcc_softc),
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};
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static devclass_t p4tcc_devclass;
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DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0);
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static int
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p4tcc_features(driver_t *driver, u_int *features)
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{
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/* Notify the ACPI CPU that we support direct access to MSRs */
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*features = ACPI_CAP_THR_MSRS;
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return (0);
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}
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static void
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p4tcc_identify(driver_t *driver, device_t parent)
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{
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if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM))
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return;
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/* Make sure we're not being doubly invoked. */
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if (device_find_child(parent, "p4tcc", -1) != NULL)
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return;
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/*
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* We attach a p4tcc child for every CPU since settings need to
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* be performed on every CPU in the SMP case. See section 13.15.3
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* of the IA32 Intel Architecture Software Developer's Manual,
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* Volume 3, for more info.
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*/
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if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL)
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device_printf(parent, "add p4tcc child failed\n");
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}
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static int
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p4tcc_probe(device_t dev)
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{
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if (resource_disabled("p4tcc", 0))
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return (ENXIO);
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device_set_desc(dev, "CPU Frequency Thermal Control");
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return (0);
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}
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static int
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p4tcc_attach(device_t dev)
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{
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struct p4tcc_softc *sc;
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struct cf_setting set;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->set_count = TCC_NUM_SETTINGS;
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/*
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* On boot, the TCC is usually in Automatic mode where reading the
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* current performance level is likely to produce bogus results.
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* We record that state here and don't trust the contents of the
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* status MSR until we've set it ourselves.
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*/
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sc->auto_mode = TRUE;
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/*
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* XXX: After a cursory glance at various Intel specification
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* XXX: updates it seems like these tests for errata is bogus.
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* XXX: As far as I can tell, the failure mode is benign, in
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* XXX: that cpus with no errata will have their bottom two
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* XXX: STPCLK# rates disabled, so rather than waste more time
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* XXX: hunting down intel docs, just document it and punt. /phk
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*/
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switch (cpu_id & 0xff) {
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case 0x22:
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case 0x24:
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case 0x25:
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case 0x27:
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case 0x29:
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/*
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* These CPU models hang when set to 12.5%.
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* See Errata O50, P44, and Z21.
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*/
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sc->set_count -= 1;
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break;
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case 0x07: /* errata N44 and P18 */
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case 0x0a:
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case 0x12:
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case 0x13:
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case 0x62: /* Pentium D B1: errata AA21 */
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case 0x64: /* Pentium D C1: errata AA21 */
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case 0x65: /* Pentium D D0: errata AA21 */
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/*
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* These CPU models hang when set to 12.5% or 25%.
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* See Errata N44, P18l and AA21.
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*/
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sc->set_count -= 2;
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break;
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}
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sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;
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/*
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* Before we finish attach, switch to 100%. It's possible the BIOS
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* set us to a lower rate. The user can override this after boot.
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*/
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set.freq = 10000;
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p4tcc_set(dev, &set);
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cpufreq_register(dev);
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return (0);
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}
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static int
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p4tcc_detach(device_t dev)
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{
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struct cf_setting set;
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int error;
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error = cpufreq_unregister(dev);
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if (error)
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return (error);
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/*
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* Before we finish detach, switch to Automatic mode.
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*/
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set.freq = 10000;
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p4tcc_set(dev, &set);
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return(0);
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}
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static int
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p4tcc_settings(device_t dev, struct cf_setting *sets, int *count)
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{
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struct p4tcc_softc *sc;
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int i, val;
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sc = device_get_softc(dev);
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if (sets == NULL || count == NULL)
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return (EINVAL);
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if (*count < sc->set_count)
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return (E2BIG);
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/* Return a list of valid settings for this driver. */
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memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);
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val = TCC_NUM_SETTINGS;
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for (i = 0; i < sc->set_count; i++, val--) {
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sets[i].freq = TCC_SPEED_PERCENT(val);
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sets[i].dev = dev;
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}
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*count = sc->set_count;
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return (0);
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}
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static int
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p4tcc_set(device_t dev, const struct cf_setting *set)
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{
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struct p4tcc_softc *sc;
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uint64_t mask, msr;
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int val;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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/*
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* Validate requested state converts to a setting that is an integer
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* from [sc->lowest_val .. TCC_NUM_SETTINGS].
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*/
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val = set->freq * TCC_NUM_SETTINGS / 10000;
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if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||
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val < sc->lowest_val || val > TCC_NUM_SETTINGS)
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return (EINVAL);
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/*
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* Read the current register and mask off the old setting and
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* On-Demand bit. If the new val is < 100%, set it and the On-Demand
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* bit, otherwise just return to Automatic mode.
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*/
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msr = rdmsr(MSR_THERM_CONTROL);
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mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;
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msr &= ~(mask | TCC_ENABLE_ONDEMAND);
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if (val < TCC_NUM_SETTINGS)
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msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND;
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wrmsr(MSR_THERM_CONTROL, msr);
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/*
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* Record whether we're now in Automatic or On-Demand mode. We have
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* to cache this since there is no reliable way to check if TCC is in
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* Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of
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* the ACPI Thermal Monitor Control Register produces 0 no matter
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* what the current mode.
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*/
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if (msr & TCC_ENABLE_ONDEMAND)
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sc->auto_mode = FALSE;
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else
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sc->auto_mode = TRUE;
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return (0);
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}
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static int
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p4tcc_get(device_t dev, struct cf_setting *set)
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{
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struct p4tcc_softc *sc;
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uint64_t msr;
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int val;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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/*
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* Read the current register and extract the current setting. If
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* in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).
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*
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* XXX This is not completely reliable since at high temperatures
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* the CPU may be automatically throttling to 50% but it's the best
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* we can do.
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*/
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if (!sc->auto_mode) {
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msr = rdmsr(MSR_THERM_CONTROL);
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val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);
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} else
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val = TCC_NUM_SETTINGS;
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memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
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set->freq = TCC_SPEED_PERCENT(val);
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set->dev = dev;
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return (0);
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}
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static int
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p4tcc_type(device_t dev, int *type)
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{
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if (type == NULL)
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return (EINVAL);
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*type = CPUFREQ_TYPE_RELATIVE;
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return (0);
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}
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