707 lines
18 KiB
C
707 lines
18 KiB
C
/*
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* Generic register and struct definitions for the BusLogic
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* MultiMaster SCSI host adapters. Product specific probe and
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* attach routines can be found in:
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* sys/dev/buslogic/bt_isa.c BT-54X, BT-445 cards
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* sys/dev/buslogic/bt_mca.c BT-64X, SDC3211B, SDC3211F
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* sys/dev/buslogic/bt_eisa.c BT-74X, BT-75x cards, SDC3222F
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* sys/dev/buslogic/bt_pci.c BT-946, BT-948, BT-956, BT-958 cards
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*
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* Copyright (c) 1998, 1999 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _BTREG_H_
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#define _BTREG_H_
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#include "bt.h"
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#include <sys/queue.h>
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#define BT_MAXTRANSFER_SIZE 0xffffffff /* limited by 32bit counter */
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#define BT_NSEG 32 /* The number of dma segments supported.
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* BT_NSEG can be maxed out at 8192 entries,
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* but the kernel will never need to transfer
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* such a large request. To reduce the
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* driver's memory consumption, we reduce the
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* max to 32. 16 would work if all transfers
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* are paged alined since the kernel will only
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* generate at most a 64k transfer, but to
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* handle non-page aligned transfers, you need
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* 17, so we round to the next power of two
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* to make allocating SG space easy and
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* efficient.
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*/
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#define ALL_TARGETS (~0)
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/*
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* Control Register pp. 1-8, 1-9 (Write Only)
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*/
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#define CONTROL_REG 0x00
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#define HARD_RESET 0x80 /* Hard Reset - return to POST state */
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#define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */
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#define RESET_INTR 0x20 /* Reset/Ack Interrupt */
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#define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */
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/*
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* Status Register pp. 1-9, 1-10 (Read Only)
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*/
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#define STATUS_REG 0x00
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#define DIAG_ACTIVE 0x80 /* Performing Internal Diags */
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#define DIAG_FAIL 0x40 /* Internal Diags failed */
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#define INIT_REQUIRED 0x20 /* MBOXes need initialization */
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#define HA_READY 0x10 /* HA ready for new commands */
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#define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */
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#define DATAIN_REG_READY 0x04 /* Data-in Byte available */
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#define STATUS_REG_RSVD 0x02
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#define CMD_INVALID 0x01 /* Invalid Command detected */
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/*
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* Command/Parameter Register pp. 1-10, 1-11 (Write Only)
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*/
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#define COMMAND_REG 0x01
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/*
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* Data in Register p. 1-11 (Read Only)
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*/
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#define DATAIN_REG 0x01
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/*
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* Interrupt Status Register pp. 1-12 -> 1-14 (Read Only)
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*/
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#define INTSTAT_REG 0x02
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#define INTR_PENDING 0x80 /* There is a pending INTR */
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#define INTSTAT_REG_RSVD 0x70
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#define SCSI_BUS_RESET 0x08 /* Bus Reset detected */
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#define CMD_COMPLETE 0x04
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#define OMB_READY 0x02 /* Outgoin Mailbox Ready */
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#define IMB_LOADED 0x01 /* Incoming Mailbox loaded */
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/*
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* Definitions for the "undocumented" geometry register
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*/
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typedef enum {
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GEOM_NODISK,
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GEOM_64x32,
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GEOM_128x32,
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GEOM_255x32
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} disk_geom_t;
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#define GEOMETRY_REG 0x03
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#define DISK0_GEOMETRY 0x03
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#define DISK1_GEOMETRY 0x0c
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#define EXTENDED_TRANSLATION 0x10
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#define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY)
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#define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2)
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#define BT_NREGS (4)
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/*
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* Opcodes for Adapter commands.
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* pp 1-18 -> 1-20
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*/
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typedef enum {
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BOP_TEST_CMDC_INTR = 0x00,
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BOP_INITIALIZE_24BMBOX = 0x01,
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BOP_START_MBOX = 0x02,
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BOP_EXECUTE_BIOS_CMD = 0x03,
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BOP_INQUIRE_BOARD_ID = 0x04,
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BOP_ENABLE_OMBR_INT = 0x05,
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BOP_SET_SEL_TIMOUT = 0x06,
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BOP_SET_TIME_ON_BUS = 0x07,
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BOP_SET_TIME_OFF_BUS = 0x08,
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BOP_SET_BUS_TRANS_RATE = 0x09,
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BOP_INQUIRE_INST_LDEVS = 0x0A,
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BOP_INQUIRE_CONFIG = 0x0B,
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BOP_ENABLE_TARGET_MODE = 0x0C,
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BOP_INQUIRE_SETUP_INFO = 0x0D,
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BOP_WRITE_LRAM = 0x1A,
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BOP_READ_LRAM = 0x1B,
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BOP_WRITE_CHIP_FIFO = 0x1C,
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BOP_READ_CHIP_FIFO = 0x1C,
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BOP_ECHO_DATA_BYTE = 0x1F,
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BOP_ADAPTER_DIAGNOSTICS = 0x20,
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BOP_SET_ADAPTER_OPTIONS = 0x21,
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BOP_INQUIRE_INST_HDEVS = 0x23,
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BOP_INQUIRE_TARG_DEVS = 0x24,
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BOP_DISABLE_HAC_INTR = 0x25,
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BOP_INITIALIZE_32BMBOX = 0x81,
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BOP_EXECUTE_SCSI_CMD = 0x83,
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BOP_INQUIRE_FW_VER_3DIG = 0x84,
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BOP_INQUIRE_FW_VER_4DIG = 0x85,
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BOP_INQUIRE_PCI_INFO = 0x86,
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BOP_INQUIRE_MODEL = 0x8B,
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BOP_TARG_SYNC_INFO = 0x8C,
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BOP_INQUIRE_ESETUP_INFO = 0x8D,
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BOP_ENABLE_STRICT_RR = 0x8F,
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BOP_STORE_LRAM = 0x90,
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BOP_FETCH_LRAM = 0x91,
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BOP_SAVE_TO_EEPROM = 0x92,
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BOP_UPLOAD_AUTO_SCSI = 0x94,
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BOP_MODIFY_IO_ADDR = 0x95,
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BOP_SET_CCB_FORMAT = 0x96,
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BOP_FLASH_ROM_DOWNLOAD = 0x97,
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BOP_FLASH_WRITE_ENABLE = 0x98,
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BOP_WRITE_INQ_BUFFER = 0x9A,
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BOP_READ_INQ_BUFFER = 0x9B,
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BOP_FLASH_UP_DOWNLOAD = 0xA7,
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BOP_READ_SCAM_DATA = 0xA8,
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BOP_WRITE_SCAM_DATA = 0xA9
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} bt_op_t;
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/************** Definitions of Multi-byte commands and responses ************/
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typedef struct {
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u_int8_t num_mboxes;
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u_int8_t base_addr[3];
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} init_24b_mbox_params_t;
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typedef struct {
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u_int8_t board_type;
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#define BOARD_TYPE_NON_MCA 0x41
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#define BOARD_TYPE_MCA 0x42
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u_int8_t cust_features;
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#define FEATURES_STANDARD 0x41
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u_int8_t firmware_rev_major;
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u_int8_t firmware_rev_minor;
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} board_id_data_t;
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typedef struct {
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u_int8_t enable;
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} enable_ombr_intr_params_t;
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typedef struct {
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u_int8_t enable;
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u_int8_t reserved;
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u_int8_t timeout[2]; /* timeout in milliseconds */
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} set_selto_parmas_t;
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typedef struct {
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u_int8_t time; /* time in milliseconds (2-15) */
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} set_timeon_bus_params_t;
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typedef struct {
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u_int8_t time; /* time in milliseconds (2-15) */
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} set_timeoff_bus_params_t;
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typedef struct {
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u_int8_t rate;
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} set_bus_trasfer_rate_params_t;
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typedef struct {
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u_int8_t targets[8];
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} installed_ldevs_data_t;
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typedef struct {
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u_int8_t dma_chan;
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#define DMA_CHAN_5 0x20
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#define DMA_CHAN_6 0x40
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#define DMA_CHAN_7 0x80
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u_int8_t irq;
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#define IRQ_9 0x01
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#define IRQ_10 0x02
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#define IRQ_11 0x04
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#define IRQ_12 0x08
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#define IRQ_14 0x20
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#define IRQ_15 0x40
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u_int8_t scsi_id;
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} config_data_t;
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typedef struct {
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u_int8_t enable;
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} target_mode_params_t;
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typedef struct {
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u_int8_t offset : 4,
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period : 3,
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sync : 1;
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} targ_syncinfo_t;
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typedef enum {
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HAB_ISA = 'A',
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HAB_MCA = 'B',
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HAB_EISA = 'C',
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HAB_NUBUS = 'D',
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HAB_VESA = 'E',
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HAB_PCI = 'F'
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} ha_type_t;
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typedef struct {
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u_int8_t initiate_sync : 1,
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parity_enable : 1,
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: 6;
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u_int8_t bus_transfer_rate;
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u_int8_t time_on_bus;
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u_int8_t time_off_bus;
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u_int8_t num_mboxes;
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u_int8_t mbox_base_addr[3];
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targ_syncinfo_t low_syncinfo[8]; /* For fast and ultra, use 8C */
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u_int8_t low_discinfo;
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u_int8_t customer_sig;
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u_int8_t letter_d;
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u_int8_t ha_type;
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u_int8_t low_wide_allowed;
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u_int8_t low_wide_active;
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targ_syncinfo_t high_syncinfo[8];
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u_int8_t high_discinfo;
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u_int8_t high_wide_allowed;
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u_int8_t high_wide_active;
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} setup_data_t;
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typedef struct {
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u_int8_t phys_addr[3];
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} write_adapter_lram_params_t;
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typedef struct {
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u_int8_t phys_addr[3];
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} read_adapter_lram_params_t;
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typedef struct {
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u_int8_t phys_addr[3];
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} write_chip_fifo_params_t;
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typedef struct {
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u_int8_t phys_addr[3];
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} read_chip_fifo_params_t;
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typedef struct {
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u_int8_t length; /* Excludes this member */
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u_int8_t low_disc_disable;
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u_int8_t low_busy_retry_disable;
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u_int8_t high_disc_disable;
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u_int8_t high_busy_retry_disable;
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} set_adapter_options_params_t;
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typedef struct {
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u_int8_t targets[8];
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} installed_hdevs_data_t;
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typedef struct {
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u_int8_t low_devs;
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u_int8_t high_devs;
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} target_devs_data_t;
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typedef struct {
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u_int8_t enable;
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} enable_hac_interrupt_params_t;
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typedef struct {
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u_int8_t num_boxes;
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u_int8_t base_addr[4];
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} init_32b_mbox_params_t;
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typedef u_int8_t fw_ver_3dig_data_t;
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typedef u_int8_t fw_ver_4dig_data_t;
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typedef struct {
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u_int8_t offset;
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u_int8_t response_len;
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} fetch_lram_params_t;
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#define AUTO_SCSI_BYTE_OFFSET 64
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typedef struct {
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u_int8_t factory_sig[2];
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u_int8_t auto_scsi_data_size; /* 2 -> 64 bytes */
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u_int8_t model_num[6];
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u_int8_t adapter_ioport;
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u_int8_t floppy_enabled :1,
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floppy_secondary :1,
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level_trigger :1,
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:2,
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system_ram_area :3;
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u_int8_t dma_channel :7,
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dma_autoconf :1;
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u_int8_t irq_channel :7,
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irq_autoconf :1;
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u_int8_t dma_trans_rate;
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u_int8_t scsi_id;
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u_int8_t low_termination :1,
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scsi_parity :1,
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high_termination :1,
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req_ack_filter :1,
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fast_sync :1,
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bus_reset :1,
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:1,
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active_negation :1;
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u_int8_t bus_on_delay;
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u_int8_t bus_off_delay;
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u_int8_t bios_enabled :1,
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int19h_redirect :1,
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extended_trans :1,
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removable_drives :1,
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:1,
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morethan2disks :1,
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interrupt_mode :1,
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floptical_support:1;
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u_int8_t low_device_enabled;
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u_int8_t high_device_enabled;
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u_int8_t low_wide_permitted;
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u_int8_t high_wide_permitted;
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u_int8_t low_fast_permitted;
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u_int8_t high_fast_permitted;
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u_int8_t low_sync_permitted;
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u_int8_t high_sync_permitted;
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u_int8_t low_disc_permitted;
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u_int8_t high_disc_permitted;
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u_int8_t low_send_start_unit;
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u_int8_t high_send_start_unit;
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u_int8_t low_ignore_in_bios_scan;
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u_int8_t high_ignore_in_bios_scan;
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u_int8_t pci_int_pin :2,
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host_ioport :2,
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round_robin :1,
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vesa_bus_over_33 :1,
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vesa_burst_write :1,
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vesa_burst_read :1;
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u_int8_t low_ultra_permitted;
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u_int8_t high_ultra_permitted;
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u_int8_t reserved[5];
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u_int8_t auto_scsi_max_lun;
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u_int8_t :1,
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scam_dominant :1,
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scam_enabled :1,
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scam_level2 :1,
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:4;
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u_int8_t int13_extensions :1,
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:1,
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cdrom_boot :1,
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:2,
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multi_boot :1,
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:2;
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u_int8_t boot_target_id :4,
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boot_channel :4;
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u_int8_t force_dev_scan :1,
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:7;
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u_int8_t low_tagged_lun_independance;
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u_int8_t high_tagged_lun_independance;
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u_int8_t low_renegotiate_after_cc;
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u_int8_t high_renegotiate_after_cc;
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u_int8_t reserverd2[10];
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u_int8_t manufacturing_diagnotic[2];
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u_int8_t checksum[2];
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} auto_scsi_data_t;
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struct bt_isa_port {
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u_int16_t addr;
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u_int8_t probed;
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u_int8_t bio;
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};
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extern struct bt_isa_port bt_isa_ports[];
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#define BT_NUM_ISAPORTS 6
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typedef enum {
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BIO_330 = 0,
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BIO_334 = 1,
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BIO_230 = 2,
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BIO_234 = 3,
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BIO_130 = 4,
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BIO_134 = 5,
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BIO_DISABLED = 6,
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BIO_DISABLED2 = 7
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} isa_compat_io_t;
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typedef struct {
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u_int8_t io_port;
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u_int8_t irq_num;
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u_int8_t low_byte_term :1,
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high_byte_term :1,
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:2,
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jp1_status :1,
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jp2_status :1,
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jp3_status :1,
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:1;
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u_int8_t reserved;
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} pci_info_data_t;
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typedef struct {
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u_int8_t ascii_model[5]; /* Fifth byte is always 0 */
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} ha_model_data_t;
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typedef struct {
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u_int8_t sync_rate[16]; /* Sync in 10ns units */
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} target_sync_info_data_t;
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typedef struct {
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u_int8_t bus_type;
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u_int8_t bios_addr;
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u_int16_t max_sg;
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u_int8_t num_mboxes;
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u_int8_t mbox_base[4];
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u_int8_t :2,
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sync_neg10MB :1,
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floppy_disable :1,
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floppy_secondary_port :1,
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burst_mode_enabled :1,
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level_trigger_ints :1,
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:1;
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u_int8_t fw_ver_bytes_2_to_4[3];
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u_int8_t wide_bus :1,
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diff_bus :1,
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scam_capable :1,
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ultra_scsi :1,
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auto_term :1,
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:3;
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} esetup_info_data_t;
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typedef struct {
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u_int32_t len;
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u_int32_t addr;
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} bt_sg_t;
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/********************** Mail Box definitions *******************************/
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typedef enum {
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BMBO_FREE = 0x0, /* MBO intry is free */
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BMBO_START = 0x1, /* MBO activate entry */
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BMBO_ABORT = 0x2 /* MBO abort entry */
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} bt_mbo_action_code_t;
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typedef struct bt_mbox_out {
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u_int32_t ccb_addr;
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u_int8_t reserved[3];
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u_int8_t action_code;
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} bt_mbox_out_t;
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typedef enum {
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BMBI_FREE = 0x0, /* MBI entry is free */
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BMBI_OK = 0x1, /* completed without error */
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BMBI_ABORT = 0x2, /* aborted ccb */
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BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */
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BMBI_ERROR = 0x4 /* Completed with error */
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} bt_mbi_comp_code_t;
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typedef struct bt_mbox_in {
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u_int32_t ccb_addr;
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u_int8_t btstat;
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u_int8_t sdstat;
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u_int8_t reserved;
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u_int8_t comp_code;
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} bt_mbox_in_t;
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/***************** Compiled Probe Information *******************************/
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struct bt_probe_info {
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int drq;
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int irq;
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};
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/****************** Hardware CCB definition *********************************/
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typedef enum {
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INITIATOR_CCB = 0x00,
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INITIATOR_SG_CCB = 0x02,
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INITIATOR_CCB_WRESID = 0x03,
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INITIATOR_SG_CCB_WRESID = 0x04,
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INITIATOR_BUS_DEV_RESET = 0x81
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} bt_ccb_opcode_t;
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typedef enum {
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BTSTAT_NOERROR = 0x00,
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BTSTAT_LINKED_CMD_COMPLETE = 0x0A,
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BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B,
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BTSTAT_DATAUNDERUN_ERROR = 0x0C,
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BTSTAT_SELTIMEOUT = 0x11,
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BTSTAT_DATARUN_ERROR = 0x12,
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BTSTAT_UNEXPECTED_BUSFREE = 0x13,
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BTSTAT_INVALID_PHASE = 0x14,
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BTSTAT_INVALID_ACTION_CODE = 0x15,
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BTSTAT_INVALID_OPCODE = 0x16,
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BTSTAT_LINKED_CCB_LUN_MISMATCH = 0x17,
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BTSTAT_INVALID_CCB_OR_SG_PARAM = 0x1A,
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BTSTAT_AUTOSENSE_FAILED = 0x1B,
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BTSTAT_TAGGED_MSG_REJECTED = 0x1C,
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BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D,
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BTSTAT_HARDWARE_FAILURE = 0x20,
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BTSTAT_TARGET_IGNORED_ATN = 0x21,
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BTSTAT_HA_SCSI_BUS_RESET = 0x22,
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BTSTAT_OTHER_SCSI_BUS_RESET = 0x23,
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BTSTAT_INVALID_RECONNECT = 0x24,
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BTSTAT_HA_BDR = 0x25,
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BTSTAT_ABORT_QUEUE_GENERATED = 0x26,
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BTSTAT_HA_SOFTWARE_ERROR = 0x27,
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BTSTAT_HA_WATCHDOG_ERROR = 0x28,
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BTSTAT_SCSI_PERROR_DETECTED = 0x30
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} btstat_t;
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struct bt_hccb {
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u_int8_t opcode;
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u_int8_t :3,
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datain :1,
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dataout :1,
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wide_tag_enable :1, /* Wide Lun CCB format */
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wide_tag_type :2; /* Wide Lun CCB format */
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u_int8_t cmd_len;
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u_int8_t sense_len;
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int32_t data_len; /* residuals can be negative */
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u_int32_t data_addr;
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u_int8_t reserved[2];
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u_int8_t btstat;
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u_int8_t sdstat;
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u_int8_t target_id;
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u_int8_t target_lun :5,
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tag_enable :1,
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tag_type :2;
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u_int8_t scsi_cdb[12];
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u_int8_t reserved2[6];
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u_int32_t sense_addr;
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};
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typedef enum {
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BCCB_FREE = 0x0,
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BCCB_ACTIVE = 0x1,
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BCCB_DEVICE_RESET = 0x2,
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BCCB_RELEASE_SIMQ = 0x4
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} bccb_flags_t;
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struct bt_ccb {
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struct bt_hccb hccb;
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SLIST_ENTRY(bt_ccb) links;
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u_int32_t flags;
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union ccb *ccb;
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bus_dmamap_t dmamap;
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bt_sg_t *sg_list;
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u_int32_t sg_list_phys;
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};
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struct sg_map_node {
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bus_dmamap_t sg_dmamap;
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bus_addr_t sg_physaddr;
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bt_sg_t* sg_vaddr;
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SLIST_ENTRY(sg_map_node) links;
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};
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struct bt_softc {
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struct device *dev;
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struct resource *port;
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struct resource *irq;
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struct resource *drq;
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void *ih;
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bus_space_tag_t tag;
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bus_space_handle_t bsh;
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struct cam_sim *sim;
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struct cam_path *path;
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bt_mbox_out_t *cur_outbox;
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bt_mbox_in_t *cur_inbox;
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bt_mbox_out_t *last_outbox;
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bt_mbox_in_t *last_inbox;
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struct bt_ccb *bt_ccb_array;
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SLIST_HEAD(,bt_ccb) free_bt_ccbs;
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LIST_HEAD(,ccb_hdr) pending_ccbs;
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u_int active_ccbs;
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u_int32_t bt_ccb_physbase;
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bt_mbox_in_t *in_boxes;
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bt_mbox_out_t *out_boxes;
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struct scsi_sense_data *sense_buffers;
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u_int32_t sense_buffers_physbase;
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struct bt_ccb *recovery_bccb;
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u_int num_boxes;
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bus_dma_tag_t parent_dmat; /*
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* All dmat's derive from
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* the dmat defined by our
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* bus.
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*/
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bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
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bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */
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bus_dmamap_t mailbox_dmamap;
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bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */
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bus_dmamap_t ccb_dmamap;
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bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
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bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
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bus_dmamap_t sense_dmamap;
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SLIST_HEAD(, sg_map_node) sg_maps;
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bus_addr_t mailbox_physbase;
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u_int num_ccbs; /* Number of CCBs malloc'd */
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u_int max_ccbs; /* Maximum allocatable CCBs */
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u_int max_sg;
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u_int unit;
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u_int scsi_id;
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u_int32_t extended_trans :1,
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wide_bus :1,
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diff_bus :1,
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ultra_scsi :1,
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extended_lun :1,
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strict_rr :1,
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tag_capable :1,
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wide_lun_ccb :1,
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resource_shortage :1,
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level_trigger_ints:1,
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:22;
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u_int16_t tags_permitted;
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u_int16_t disc_permitted;
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u_int16_t sync_permitted;
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u_int16_t fast_permitted;
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u_int16_t ultra_permitted;
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u_int16_t wide_permitted;
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u_int8_t init_level;
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volatile u_int8_t command_cmp;
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volatile u_int8_t latched_status;
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u_int32_t bios_addr;
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char firmware_ver[6];
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char model[5];
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};
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extern u_long bt_unit;
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#define BT_TEMP_UNIT 0xFF /* Unit for probes */
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void bt_init_softc(device_t dev,
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struct resource *port,
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struct resource *irq,
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struct resource *drq);
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void bt_free_softc(device_t dev);
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int bt_port_probe(device_t dev,
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struct bt_probe_info *info);
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int bt_probe(device_t dev);
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int bt_fetch_adapter_info(device_t dev);
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int bt_init(device_t dev);
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int bt_attach(device_t dev);
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void bt_intr(void *arg);
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int bt_check_probed_iop(u_int ioport);
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void bt_mark_probed_bio(isa_compat_io_t port);
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void bt_mark_probed_iop(u_int ioport);
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void bt_find_probe_range(int ioport,
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int *port_index,
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int *max_port_index);
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int bt_iop_from_bio(isa_compat_io_t bio_index);
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#define DEFAULT_CMD_TIMEOUT 100000 /* 10 sec */
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int bt_cmd(struct bt_softc *bt, bt_op_t opcode,
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u_int8_t *params, u_int param_len,
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u_int8_t *reply_data, u_int reply_len,
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u_int cmd_timeout);
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#define bt_name(bt) device_get_nameunit(bt->dev)
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#define bt_inb(bt, port) \
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bus_space_read_1((bt)->tag, (bt)->bsh, port)
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#define bt_outb(bt, port, value) \
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bus_space_write_1((bt)->tag, (bt)->bsh, port, value)
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#endif /* _BT_H_ */
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