c92e45e4a1
Appologies for making this one bulk commit, but I have tested all these changes together and don't want to break anything by trying to disentangle it. o Make debugging a sysctl/tunable o Remove flags word from yenta chip info, it is unused o Make 16-bit card I/O range and 32-bit card I/O range tunables o Start the rename of pccbb to cbb to match NetBSD by misc renames. o Kill the now bogus list of softcs to create kthread. Instead, just create the kthread in the attach routine. o Remove sc_ from some structure names. It isn't needed. o Refine chipset lookup code. o Match generic PCI <-> CardBus bridges. We specifically don't generically match PCI PCMCIA bridges because they are not, with one exception, yenta devices. o Add some comments about the why we need to have a function table ala OLDCARD o The PCI interrupt routing by using the ExCA registers is needed for for all bridges, per the spec, not just TI ones. o Collapse TOPIC95 and TOPIC95B. o Using the ToPIC 97 and 100 datasheets, try to support these bridges better, but more work is needed. o Generally clarify some XXX comments and add them in a few places where things didn't look right to me. o Move interrupt generating register access until after we establish an ISR. o Add support for YV and XV cards. X and Y are numbers to be determined later (but maybe never). o factor powerup code for 16-bit and 32-bit cards. o When a card supports more than one voltage, prefer the lowest supported volage. Windows does this, and MS's design guides imply this is the right thing to do. o Document race between kthread_exit(0) and kldunload's unmapping of pages that John Baldwin and I discovered. o Debounce the CSC interrupt a little better. o When a 16-bit card is inserted when we don't have a pccard child, warn about it better. Ditto for 32-bit card. o Ack ALL the interrupt bits that we get, not just 0x1. o maybe a couple minor style nits corrected.
183 lines
7.0 KiB
C
183 lines
7.0 KiB
C
/*
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* Copyright (c) 2000,2001 Jonathan Chen.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Register definitions for PCI to Cardbus Bridge chips
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*/
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/* PCI header registers */
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#define CBBR_SOCKBASE 0x10 /* len=4 */
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#define CBBR_MEMBASE0 0x1c /* len=4 */
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#define CBBR_MEMLIMIT0 0x20 /* len=4 */
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#define CBBR_MEMBASE1 0x24 /* len=4 */
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#define CBBR_MEMLIMIT1 0x28 /* len=4 */
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#define CBBR_IOBASE0 0x2c /* len=4 */
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#define CBBR_IOLIMIT0 0x30 /* len=4 */
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#define CBBR_IOBASE1 0x34 /* len=4 */
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#define CBBR_IOLIMIT1 0x38 /* len=4 */
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#define CBB_MEMALIGN 4096
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#define CBB_IOALIGN 4
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#define CBBR_INTRLINE 0x3c /* len=1 */
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#define CBBR_INTRPIN 0x3d /* len=1 */
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#define CBBR_BRIDGECTRL 0x3e /* len=2 */
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# define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020
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# define CBBM_BRIDGECTRL_RESET 0x0040
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# define CBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080
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# define CBBM_BRIDGECTRL_PREFETCH_0 0x0100
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# define CBBM_BRIDGECTRL_PREFETCH_1 0x0200
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# define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400
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/* additional bit for RF5C46[567] */
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# define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800
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# define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000
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#define CBBR_LEGACY 0x44 /* len=4 */
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#define CBBR_CBCTRL 0x91 /* len=1 */
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/* bits for TI 113X */
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# define CBBM_CBCTRL_113X_RI_EN 0x80
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# define CBBM_CBCTRL_113X_ZV_EN 0x40
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# define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20
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# define CBBM_CBCTRL_113X_PCI_INTR 0x10
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# define CBBM_CBCTRL_113X_PCI_CSC 0x08
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# define CBBM_CBCTRL_113X_PCI_CSC_D 0x04
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# define CBBM_CBCTRL_113X_SPEAKER_EN 0x02
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# define CBBM_CBCTRL_113X_INTR_DET 0x01
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/* bits for TI 12XX */
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# define CBBM_CBCTRL_12XX_RI_EN 0x80
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# define CBBM_CBCTRL_12XX_ZV_EN 0x40
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# define CBBM_CBCTRL_12XX_AUD2MUX 0x04
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# define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02
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# define CBBM_CBCTRL_12XX_INTR_DET 0x01
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#define CBBR_DEVCTRL 0x92 /* len=1 */
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# define CBBM_DEVCTRL_INT_SERIAL 0x04
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# define CBBM_DEVCTRL_INT_PCI 0x02
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/* ToPIC 95 ONLY */
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#define CBBR_TOPIC_SOCKETCTRL 0x90
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# define CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
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/* ToPIC 97, 100 */
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#define CBBR_TOPIC_ZV_CONTROL 0x9c /* 1 byte */
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# define CBBM_TOPIC_ZVC_ENABLE 0x1
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/* TOPIC 95+ */
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#define CBBR_TOPIC_SLOTCTRL 0xa0 /* 1 byte */
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# define CBBM_TOPIC_SLOTCTRL_SLOTON 0x80
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# define CBBM_TOPIC_SLOTCTRL_SLOTEN 0x40
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# define CBBM_TOPIC_SLOTCTRL_ID_LOCK 0x20
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# define CBBM_TOPIC_SLOTCTRL_ID_WP 0x10
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# define CBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0c
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# define CBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2
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# define CBBM_TOPIC_SLOTCTRL_OSF_MASK 0x03
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# define CBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0
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/* TOPIC 95+ */
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#define CBBR_TOPIC_INTCTRL 0xa1 /* 1 byte */
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# define CBBM_TOPIC_INTCTRL_INTB 0x20
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# define CBBM_TOPIC_INTCTRL_INTA 0x10
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# define CBBM_TOPIC_INTCTRL_INT_MASK 0x30
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/* The following bits may be for ToPIC 95 only */
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# define CBBM_TOPIC_INTCTRL_CLOCK_MASK 0x0c
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# define CBBM_TOPIC_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */
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# define CBBM_TOPIC_INTCTRL_CLOCK_1 0x04 /* PCI Clk */
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# define CBBM_TOPIC_INTCTRL_CLOCK_0 0x00 /* no clock */
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/* ToPIC97, 100 defines the following bits */
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# define CBBM_TOPIC_INTCTRL_STSIRQNP 0x04
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# define CBBM_TOPIC_INTCTRL_IRQNP 0x02
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# define CBBM_TOPIC_INTCTRL_INTIRQSEL 0x01
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/* TOPIC 95+ */
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#define CBBR_TOPIC_CDC 0xa3 /* 1 byte */
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# define CBBM_TOPIC_CDC_CARDBUS 0x80
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# define CBBM_TOPIC_CDC_VS1 0x04
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# define CBBM_TOPIC_CDC_VS2 0x02
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# define CBBM_TOPIC_CDC_SWDETECT 0x01
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/* Socket definitions */
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#define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */
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#define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */
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#define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */
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#define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */
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#define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */
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#define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */
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#define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */
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#define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */
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#define CBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */
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#define CBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */
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#define CBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */
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#define CBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */
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#define CBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */
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#define CBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */
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#define CBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */
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#define CBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */
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#define CBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */
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#define CBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */
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#define CBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */
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#define CBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */
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#define CBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */
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#define CBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */
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#define CBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */
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#define CBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */
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#define CBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */
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#define CBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */
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#define CBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */
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#define CBB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */
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#define CBB_SOCKET_CTRL_VPPMASK 0x07
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#define CBB_SOCKET_CTRL_VPP_OFF 0x00
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#define CBB_SOCKET_CTRL_VPP_12V 0x01
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#define CBB_SOCKET_CTRL_VPP_5V 0x02
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#define CBB_SOCKET_CTRL_VPP_3V 0x03
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#define CBB_SOCKET_CTRL_VPP_XV 0x04
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#define CBB_SOCKET_CTRL_VPP_YV 0x05
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#define CBB_SOCKET_CTRL_VCCMASK 0x70
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#define CBB_SOCKET_CTRL_VCC_OFF 0x00
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#define CBB_SOCKET_CTRL_VCC_5V 0x20
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#define CBB_SOCKET_CTRL_VCC_3V 0x30
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#define CBB_SOCKET_CTRL_VCC_XV 0x40
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#define CBB_SOCKET_CTRL_VCC_YV 0x50
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#define CBB_SOCKET_CTRL_STOPCLK 0x80
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#include <dev/pccbb/pccbbdevid.h>
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#define CBB_SOCKET_EVENT 0x00
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#define CBB_SOCKET_MASK 0x04
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#define CBB_SOCKET_STATE 0x08
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#define CBB_SOCKET_FORCE 0x0c
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#define CBB_SOCKET_CONTROL 0x10
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#define CBB_SOCKET_POWER 0x14
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