51 lines
2.0 KiB
C
51 lines
2.0 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_ATH_AR5311REG_H_
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#define _DEV_ATH_AR5311REG_H_
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/*
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* Definitions for the Atheros 5311 chipset.
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*/
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#define AR5311_QDCLKGATE 0x005c /* MAC QCU/DCU clock gating control */
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#define AR5311_QDCLKGATE_QCU_M 0x0000FFFF /* QCU clock disable */
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#define AR5311_QDCLKGATE_DCU_M 0x07FF0000 /* DCU clock disable */
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#define AR5311_RXCFG_DEF_RX_ANTENNA 0x00000008 /* Default Receive Antenna */
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/*
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* NOTE: MAC_5211/MAC_5311 difference
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* On Oahu the TX latency field has increased from 6 bits to 9 bits.
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* The RX latency field is unchanged but is shifted over 3 bits.
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*/
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#define AR5311_USEC_TX_LAT_M 0x000FC000 /* tx latency (usec) */
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#define AR5311_USEC_TX_LAT_S 14
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#define AR5311_USEC_RX_LAT_M 0x03F00000 /* rx latency (usec) */
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#define AR5311_USEC_RX_LAT_S 20
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/*
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* NOTE: MAC_5211/MAC_5311 difference
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* On Maui2/Spirit the frame sequence number is controlled per DCU.
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* On Oahu the frame sequence number is global across all DCUs and
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* is controlled
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*/
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#define AR5311_D_MISC_SEQ_NUM_CONTROL 0x01000000 /* seq num local or global */
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#define AR5311_DIAG_USE_ECO 0x00000400 /* "super secret" enable ECO */
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#endif /* _DEV_ATH_AR5311REG_H_ */
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