57e87ccecb
counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
110 lines
4.3 KiB
C
110 lines
4.3 KiB
C
/*-
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* Copyright (c) 1999 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: iommuvar.h,v 1.9 2001/07/20 00:07:13 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_IOMMUVAR_H_
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#define _MACHINE_IOMMUVAR_H_
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#define IO_PAGE_SIZE PAGE_SIZE_8K
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#define IO_PAGE_MASK PAGE_MASK_8K
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#define IO_PAGE_SHIFT PAGE_SHIFT_8K
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#define round_io_page(x) round_page(x)
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#define trunc_io_page(x) trunc_page(x)
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/*
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* LRU queue handling for lazy resource allocation
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*/
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TAILQ_HEAD(iommu_maplruq_head, bus_dmamap);
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/*
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* Per-IOMMU state. The parenthesized comments indicate the locking strategy:
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* i - protected by is_mtx.
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* r - read-only after initialization.
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* * - comment refers to pointer target / target hardware registers
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* (for bus_addr_t).
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* is_maplruq is also locked by is_mtx. Elements of is_tsb may only be
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* accessed from functions operating on the map owning the corresponding
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* resource, so the locking the user is required to do to protect the
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* map is sufficient.
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* dm_reslist of all maps are locked by is_mtx as well.
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* is_dvma_rman has its own internal lock.
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*/
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struct iommu_state {
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struct mtx is_mtx;
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struct rman is_dvma_rman; /* DVMA space rman */
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struct iommu_maplruq_head is_maplruq; /* (i) LRU queue */
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vm_paddr_t is_ptsb; /* (r) TSB physical address */
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uint64_t *is_tsb; /* (*i) TSB virtual address */
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int is_tsbsize; /* (r) 0 = 8K, ... */
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uint64_t is_pmaxaddr; /* (r) max. physical address */
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uint64_t is_dvmabase; /* (r) */
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int64_t is_cr; /* (r) Control reg value */
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vm_paddr_t is_flushpa[2]; /* (r) */
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volatile int64_t *is_flushva[2]; /* (r, *i) */
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/*
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* (i)
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* When a flush is completed, 64 bytes will be stored at the given
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* location, the first double word being 1, to indicate completion.
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* The lower 6 address bits are ignored, so the addresses need to be
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* suitably aligned; over-allocate a large enough margin to be able
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* to adjust it.
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* Two such buffers are needed.
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*/
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volatile char is_flush[STRBUF_FLUSHSYNC_NBYTES * 3 - 1];
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/* copies of our parents state, to allow us to be self contained */
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bus_space_tag_t is_bustag; /* (r) Our bus tag */
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bus_space_handle_t is_bushandle; /* (r) */
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bus_addr_t is_iommu; /* (r, *i) IOMMU registers */
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bus_addr_t is_sb[2]; /* (r, *i) Streaming buffer */
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/* Tag diagnostics access */
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bus_addr_t is_dtag; /* (r, *r) */
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/* Data RAM diagnostic access */
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bus_addr_t is_ddram; /* (r, *r) */
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/* LRU queue diag. access */
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bus_addr_t is_dqueue; /* (r, *r) */
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/* Virtual address diagnostics register */
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bus_addr_t is_dva; /* (r, *r) */
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/* Tag compare diagnostics access */
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bus_addr_t is_dtcmp; /* (r, *r) */
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};
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/* interfaces for PCI/SBus code */
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void iommu_init(const char *name, struct iommu_state *is, int tsbsize,
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uint32_t iovabase, int resvpg);
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void iommu_reset(struct iommu_state *is);
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void iommu_decode_fault(struct iommu_state *is, vm_offset_t phys);
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extern struct bus_dma_methods iommu_dma_methods;
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#endif /* !_MACHINE_IOMMUVAR_H_ */
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