220 lines
8.6 KiB
C
220 lines
8.6 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_ATH_DESC_H
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#define _DEV_ATH_DESC_H
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#include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */
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/*
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* Transmit descriptor status. This structure is filled
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* in only after the tx descriptor process method finds a
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* ``done'' descriptor; at which point it returns something
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* other than HAL_EINPROGRESS.
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*
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* Note that ts_antenna may not be valid for all h/w. It
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* should be used only if non-zero.
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*/
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struct ath_tx_status {
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uint16_t ts_seqnum; /* h/w assigned sequence number */
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uint16_t ts_tstamp; /* h/w assigned timestamp */
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uint8_t ts_status; /* frame status, 0 => xmit ok */
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uint8_t ts_rate; /* h/w transmit rate index */
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int8_t ts_rssi; /* tx ack RSSI */
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uint8_t ts_shortretry; /* # short retries */
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uint8_t ts_longretry; /* # long retries */
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uint8_t ts_virtcol; /* virtual collision count */
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uint8_t ts_antenna; /* antenna information */
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uint8_t ts_finaltsi; /* final transmit series index */
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#ifdef AH_SUPPORT_AR5416
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/* 802.11n status */
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uint8_t ts_flags; /* misc flags */
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int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
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int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
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/* #define ts_rssi ts_rssi_combined */
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uint32_t ts_ba_low; /* blockack bitmap low */
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uint32_t ts_ba_high; /* blockack bitmap high */
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uint32_t ts_evm0; /* evm bytes */
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uint32_t ts_evm1;
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uint32_t ts_evm2;
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#endif /* AH_SUPPORT_AR5416 */
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};
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/* bits found in ts_status */
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#define HAL_TXERR_XRETRY 0x01 /* excessive retries */
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#define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */
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#define HAL_TXERR_FIFO 0x04 /* fifo underrun */
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#define HAL_TXERR_XTXOP 0x08 /* txop exceeded */
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#define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */
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/* bits found in ts_flags */
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#define HAL_TX_BA 0x01 /* Block Ack seen */
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#define HAL_TX_AGGR 0x02 /* Aggregate */
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#define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */
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#define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */
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#define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */
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/*
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* Receive descriptor status. This structure is filled
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* in only after the rx descriptor process method finds a
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* ``done'' descriptor; at which point it returns something
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* other than HAL_EINPROGRESS.
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*
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* If rx_status is zero, then the frame was received ok;
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* otherwise the error information is indicated and rs_phyerr
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* contains a phy error code if HAL_RXERR_PHY is set. In general
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* the frame contents is undefined when an error occurred thought
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* for some errors (e.g. a decryption error), it may be meaningful.
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*
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* Note that the receive timestamp is expanded using the TSF to
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* at least 15 bits (regardless of what the h/w provides directly).
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* Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
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* find out if the hardware is capable.
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*
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* rx_rssi is in units of dbm above the noise floor. This value
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* is measured during the preamble and PLCP; i.e. with the initial
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* 4us of detection. The noise floor is typically a consistent
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* -96dBm absolute power in a 20MHz channel.
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*/
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struct ath_rx_status {
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uint16_t rs_datalen; /* rx frame length */
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uint8_t rs_status; /* rx status, 0 => recv ok */
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uint8_t rs_phyerr; /* phy error code */
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int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */
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uint8_t rs_keyix; /* key cache index */
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uint8_t rs_rate; /* h/w receive rate index */
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uint8_t rs_more; /* more descriptors follow */
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uint32_t rs_tstamp; /* h/w assigned timestamp */
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uint32_t rs_antenna; /* antenna information */
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#ifdef AH_SUPPORT_AR5416
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/* 802.11n status */
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int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */
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int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
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uint8_t rs_isaggr; /* is part of the aggregate */
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uint8_t rs_moreaggr; /* more frames in aggr to follow */
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uint8_t rs_num_delims; /* number of delims in aggr */
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uint8_t rs_flags; /* misc flags */
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uint32_t rs_evm0; /* evm bytes */
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uint32_t rs_evm1;
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uint32_t rs_evm2;
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#endif /* AH_SUPPORT_AR5416 */
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};
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/* bits found in rs_status */
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#define HAL_RXERR_CRC 0x01 /* CRC error on frame */
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#define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
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#define HAL_RXERR_FIFO 0x04 /* fifo overrun */
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#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
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#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
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/* bits found in rs_flags */
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#define HAL_RX_MORE 0x01 /* more descriptors follow */
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#define HAL_RX_MORE_AGGR 0x02 /* more frames in aggr */
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#define HAL_RX_GI 0x04 /* full gi */
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#define HAL_RX_2040 0x08 /* 40 Mhz */
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#define HAL_RX_DELIM_CRC_PRE 0x10 /* crc error in delimiter pre */
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#define HAL_RX_DELIM_CRC_POST 0x20 /* crc error in delim after */
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#define HAL_RX_DECRYPT_BUSY 0x40 /* decrypt was too slow */
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#define HAL_RX_HI_RX_CHAIN 0x80 /* SM power save: hi Rx chain control */
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enum {
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HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
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HAL_PHYERR_TIMING = 1, /* Timing error */
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HAL_PHYERR_PARITY = 2, /* Illegal parity */
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HAL_PHYERR_RATE = 3, /* Illegal rate */
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HAL_PHYERR_LENGTH = 4, /* Illegal length */
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HAL_PHYERR_RADAR = 5, /* Radar detect */
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HAL_PHYERR_SERVICE = 6, /* Illegal service */
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HAL_PHYERR_TOR = 7, /* Transmit override receive */
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/* NB: these are specific to the 5212 */
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HAL_PHYERR_OFDM_TIMING = 17, /* */
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HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */
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HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */
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HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */
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HAL_PHYERR_OFDM_POWER_DROP = 21, /* */
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HAL_PHYERR_OFDM_SERVICE = 22, /* */
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HAL_PHYERR_OFDM_RESTART = 23, /* */
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HAL_PHYERR_CCK_TIMING = 25, /* */
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HAL_PHYERR_CCK_HEADER_CRC = 26, /* */
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HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */
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HAL_PHYERR_CCK_SERVICE = 30, /* */
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HAL_PHYERR_CCK_RESTART = 31, /* */
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};
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/* value found in rs_keyix to mark invalid entries */
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#define HAL_RXKEYIX_INVALID ((uint8_t) -1)
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/* value used to specify no encryption key for xmit */
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#define HAL_TXKEYIX_INVALID ((u_int) -1)
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/* XXX rs_antenna definitions */
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/*
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* Definitions for the software frame/packet descriptors used by
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* the Atheros HAL. This definition obscures hardware-specific
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* details from the driver. Drivers are expected to fillin the
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* portions of a descriptor that are not opaque then use HAL calls
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* to complete the work. Status for completed frames is returned
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* in a device-independent format.
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*/
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#ifdef AH_SUPPORT_AR5416
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#define HAL_DESC_HW_SIZE 20
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#else
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#define HAL_DESC_HW_SIZE 4
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#endif /* AH_SUPPORT_AR5416 */
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struct ath_desc {
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/*
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* The following definitions are passed directly
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* the hardware and managed by the HAL. Drivers
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* should not touch those elements marked opaque.
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*/
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uint32_t ds_link; /* phys address of next descriptor */
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uint32_t ds_data; /* phys address of data buffer */
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uint32_t ds_ctl0; /* opaque DMA control 0 */
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uint32_t ds_ctl1; /* opaque DMA control 1 */
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uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */
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};
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struct ath_desc_status {
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union {
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struct ath_tx_status tx;/* xmit status */
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struct ath_rx_status rx;/* recv status */
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} ds_us;
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};
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#define ds_txstat ds_us.tx
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#define ds_rxstat ds_us.rx
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/* flags passed to tx descriptor setup methods */
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#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
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#define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
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#define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
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#define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */
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#define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
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#define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */
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/* NB: this only affects frame, not any RTS/CTS */
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#define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
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#define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */
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#define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */
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#define HAL_TXDESC_VMF 0x0200 /* virtual more frag */
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/* flags passed to rx descriptor setup methods */
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#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
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#endif /* _DEV_ATH_DESC_H */
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