8d11dd01a1
this change is to improve concurrency: - Drop global state stored in the shadow overflow page table (and all other global state) - Remove all global locks - Use per-PTE lock bits to allow parallel page insertion - Reconstruct state when requested for evicted PTEs instead of buffering it during overflow This drops total wall time for make buildworld on a 32-thread POWER8 system by a factor of two and system time by a factor of three, providing performance 20% better than similarly clocked Core i7 Xeons per-core. Performance on smaller SMP systems, where PMAP lock contention was not as much of an issue, is nearly unchanged. Tested on: POWER8, POWER5+, G5 UP, G5 SMP (64-bit and 32-bit kernels) Merged from: user/nwhitehorn/ppc64-pmap-rework Looked over by: jhibbits, andreast MFC after: 3 months Relnotes: yes Sponsored by: FreeBSD Foundation
284 lines
7.2 KiB
C
284 lines
7.2 KiB
C
/*-
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* Copyright (C) 2010 Nathan Whitehorn
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/lock.h>
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#include <sys/msgbuf.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <sys/vmmeter.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_page.h>
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#include <vm/vm_map.h>
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#include <vm/vm_object.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_pageout.h>
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#include <vm/uma.h>
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#include <powerpc/aim/mmu_oea64.h>
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#include "mmu_if.h"
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#include "moea64_if.h"
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#include "ps3-hvcall.h"
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#define VSID_HASH_MASK 0x0000007fffffffffUL
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#define PTESYNC() __asm __volatile("ptesync")
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extern int ps3fb_remap(void);
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static uint64_t mps3_vas_id;
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/*
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* Kernel MMU interface
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*/
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static void mps3_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
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vm_offset_t kernelend);
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static void mps3_cpu_bootstrap(mmu_t mmup, int ap);
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static int64_t mps3_pte_synch(mmu_t, struct pvo_entry *);
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static int64_t mps3_pte_clear(mmu_t, struct pvo_entry *, uint64_t ptebit);
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static int64_t mps3_pte_unset(mmu_t, struct pvo_entry *);
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static int mps3_pte_insert(mmu_t, struct pvo_entry *);
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static mmu_method_t mps3_methods[] = {
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MMUMETHOD(mmu_bootstrap, mps3_bootstrap),
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MMUMETHOD(mmu_cpu_bootstrap, mps3_cpu_bootstrap),
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MMUMETHOD(moea64_pte_synch, mps3_pte_synch),
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MMUMETHOD(moea64_pte_clear, mps3_pte_clear),
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MMUMETHOD(moea64_pte_unset, mps3_pte_unset),
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MMUMETHOD(moea64_pte_insert, mps3_pte_insert),
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{ 0, 0 }
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};
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MMU_DEF_INHERIT(ps3_mmu, "mmu_ps3", mps3_methods, 0, oea64_mmu);
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static struct mtx mps3_table_lock;
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static void
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mps3_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
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{
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uint64_t final_pteg_count;
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mtx_init(&mps3_table_lock, "page table", NULL, MTX_DEF);
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moea64_early_bootstrap(mmup, kernelstart, kernelend);
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lv1_construct_virtual_address_space(
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20 /* log_2(moea64_pteg_count) */, 2 /* n page sizes */,
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(24UL << 56) | (16UL << 48) /* page sizes 16 MB + 64 KB */,
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&mps3_vas_id, &final_pteg_count
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);
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moea64_pteg_count = final_pteg_count / sizeof(struct lpteg);
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moea64_mid_bootstrap(mmup, kernelstart, kernelend);
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moea64_late_bootstrap(mmup, kernelstart, kernelend);
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}
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static void
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mps3_cpu_bootstrap(mmu_t mmup, int ap)
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{
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struct slb *slb = PCPU_GET(slb);
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register_t seg0;
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int i;
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mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR);
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/*
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* Destroy the loader's address space if we are coming up for
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* the first time, and redo the FB mapping so we can continue
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* having a console.
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*/
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if (!ap)
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lv1_destruct_virtual_address_space(0);
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lv1_select_virtual_address_space(mps3_vas_id);
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if (!ap)
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ps3fb_remap();
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/*
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* Install kernel SLB entries
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*/
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__asm __volatile ("slbia");
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__asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : "r"(0));
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for (i = 0; i < 64; i++) {
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if (!(slb[i].slbe & SLBE_VALID))
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continue;
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__asm __volatile ("slbmte %0, %1" ::
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"r"(slb[i].slbv), "r"(slb[i].slbe));
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}
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}
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static int64_t
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mps3_pte_synch_locked(struct pvo_entry *pvo)
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{
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uint64_t halfbucket[4], rcbits;
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PTESYNC();
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lv1_read_htab_entries(mps3_vas_id, pvo->pvo_pte.slot & ~0x3UL,
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&halfbucket[0], &halfbucket[1], &halfbucket[2], &halfbucket[3],
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&rcbits);
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/* Check if present in page table */
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if ((halfbucket[pvo->pvo_pte.slot & 0x3] & LPTE_AVPN_MASK) !=
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((pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) &
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LPTE_AVPN_MASK))
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return (-1);
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if (!(halfbucket[pvo->pvo_pte.slot & 0x3] & LPTE_VALID))
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return (-1);
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/*
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* rcbits contains the low 12 bits of each PTE's 2nd part,
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* spaced at 16-bit intervals
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*/
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return ((rcbits >> ((3 - (pvo->pvo_pte.slot & 0x3))*16)) &
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(LPTE_CHG | LPTE_REF));
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}
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static int64_t
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mps3_pte_synch(mmu_t mmu, struct pvo_entry *pvo)
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{
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int64_t retval;
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mtx_lock(&mps3_table_lock);
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retval = mps3_pte_synch_locked(pvo);
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mtx_unlock(&mps3_table_lock);
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return (retval);
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}
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static int64_t
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mps3_pte_clear(mmu_t mmu, struct pvo_entry *pvo, uint64_t ptebit)
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{
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int64_t refchg;
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struct lpte pte;
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mtx_lock(&mps3_table_lock);
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refchg = mps3_pte_synch_locked(pvo);
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if (refchg < 0) {
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mtx_unlock(&mps3_table_lock);
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return (refchg);
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}
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moea64_pte_from_pvo(pvo, &pte);
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pte.pte_lo |= refchg;
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pte.pte_lo &= ~ptebit;
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/* XXX: race on RC bits between write and sync. Anything to do? */
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lv1_write_htab_entry(mps3_vas_id, pvo->pvo_pte.slot, pte.pte_hi,
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pte.pte_lo);
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mtx_unlock(&mps3_table_lock);
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return (refchg);
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}
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static int64_t
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mps3_pte_unset(mmu_t mmu, struct pvo_entry *pvo)
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{
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int64_t refchg;
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mtx_lock(&mps3_table_lock);
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refchg = mps3_pte_synch_locked(pvo);
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if (refchg < 0) {
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moea64_pte_overflow--;
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mtx_unlock(&mps3_table_lock);
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return (-1);
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}
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/* XXX: race on RC bits between unset and sync. Anything to do? */
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lv1_write_htab_entry(mps3_vas_id, pvo->pvo_pte.slot, 0, 0);
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mtx_unlock(&mps3_table_lock);
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moea64_pte_valid--;
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return (refchg & (LPTE_REF | LPTE_CHG));
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}
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static int
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mps3_pte_insert(mmu_t mmu, struct pvo_entry *pvo)
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{
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int result;
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struct lpte pte, evicted;
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uint64_t index;
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if (pvo->pvo_vaddr & PVO_HID) {
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/* Hypercall needs primary PTEG */
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pvo->pvo_vaddr &= ~PVO_HID;
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pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3);
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}
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pvo->pvo_pte.slot &= ~7UL;
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moea64_pte_from_pvo(pvo, &pte);
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evicted.pte_hi = 0;
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PTESYNC();
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mtx_lock(&mps3_table_lock);
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result = lv1_insert_htab_entry(mps3_vas_id, pvo->pvo_pte.slot,
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pte.pte_hi, pte.pte_lo, LPTE_LOCKED | LPTE_WIRED, 0,
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&index, &evicted.pte_hi, &evicted.pte_lo);
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mtx_unlock(&mps3_table_lock);
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if (result != 0) {
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/* No freeable slots in either PTEG? We're hosed. */
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panic("mps3_pte_insert: overflow (%d)", result);
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return (-1);
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}
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/*
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* See where we ended up.
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*/
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if ((index & ~7UL) != pvo->pvo_pte.slot)
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pvo->pvo_vaddr |= PVO_HID;
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pvo->pvo_pte.slot = index;
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moea64_pte_valid++;
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if (evicted.pte_hi) {
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KASSERT((evicted.pte_hi & (LPTE_WIRED | LPTE_LOCKED)) == 0,
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("Evicted a wired PTE"));
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moea64_pte_valid--;
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moea64_pte_overflow++;
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}
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return (0);
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}
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