1667 lines
40 KiB
C
1667 lines
40 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $FreeBSD$
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*/
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/*
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* Routines to handle clock hardware.
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*/
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/*
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* inittodr, settodr and support routines written
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* by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
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*
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* reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
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*/
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/*
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* modified for PC98 by Kakefuda
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*/
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#include "opt_clock.h"
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#include "opt_isa.h"
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#include "opt_mca.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/time.h>
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#include <sys/timetc.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/cons.h>
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#include <sys/power.h>
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#include <machine/clock.h>
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#ifdef CLK_CALIBRATION_LOOP
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#endif
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#include <machine/cputypes.h>
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#include <machine/frame.h>
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#include <machine/limits.h>
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#include <machine/md_var.h>
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#include <machine/psl.h>
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#ifdef APIC_IO
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#include <machine/segments.h>
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#endif
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#if defined(SMP) || defined(APIC_IO)
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#include <machine/smp.h>
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#endif /* SMP || APIC_IO */
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#include <machine/specialreg.h>
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#include <i386/isa/icu.h>
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#include <pc98/pc98/pc98_machdep.h>
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#include <i386/isa/isa_device.h>
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#else
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#include <i386/isa/isa.h>
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#include <isa/rtc.h>
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#endif
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#ifdef DEV_ISA
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#include <isa/isavar.h>
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#endif
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#include <i386/isa/timerreg.h>
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#include <i386/isa/intr_machdep.h>
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#ifdef DEV_MCA
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#include <i386/isa/mca_machdep.h>
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#endif
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#ifdef APIC_IO
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#include <i386/isa/intr_machdep.h>
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/* The interrupt triggered by the 8254 (timer) chip */
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int apic_8254_intr;
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static u_long read_intr_count __P((int vec));
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static void setup_8254_mixed_mode __P((void));
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#endif
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/*
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* 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
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* can use a simple formula for leap years.
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*/
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#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
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#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
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#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
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/*
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* Time in timer cycles that it takes for microtime() to disable interrupts
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* and latch the count. microtime() currently uses "cli; outb ..." so it
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* normally takes less than 2 timer cycles. Add a few for cache misses.
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* Add a few more to allow for latency in bogus calls to microtime() with
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* interrupts already disabled.
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*/
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#define TIMER0_LATCH_COUNT 20
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/*
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* Maximum frequency that we are willing to allow for timer0. Must be
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* low enough to guarantee that the timer interrupt handler returns
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* before the next timer interrupt.
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*/
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#define TIMER0_MAX_FREQ 20000
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int adjkerntz; /* local offset from GMT in seconds */
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int clkintr_pending;
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int disable_rtc_set; /* disable resettodr() if != 0 */
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int statclock_disable;
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#ifndef TIMER_FREQ
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#ifdef PC98
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#define TIMER_FREQ 2457600
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#else /* IBM-PC */
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#define TIMER_FREQ 1193182
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#endif /* PC98 */
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#endif
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u_int timer_freq = TIMER_FREQ;
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int timer0_max_count;
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u_int tsc_freq;
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int tsc_is_broken;
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u_int tsc_present;
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int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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struct mtx clock_lock;
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static int beeping = 0;
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static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
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static u_int hardclock_max_count;
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static u_int32_t i8254_lastcount;
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static u_int32_t i8254_offset;
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static int i8254_ticked;
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/*
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* XXX new_function and timer_func should not handle clockframes, but
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* timer_func currently needs to hold hardclock to handle the
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* timer0_state == 0 case. We should use inthand_add()/inthand_remove()
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* to switch between clkintr() and a slightly different timerintr().
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*/
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static void (*new_function) __P((struct clockframe *frame));
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static u_int new_rate;
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#ifndef PC98
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static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
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static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
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#endif
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static u_int timer0_prescaler_count;
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/* Values for timerX_state: */
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#define RELEASED 0
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#define RELEASE_PENDING 1
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#define ACQUIRED 2
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#define ACQUIRE_PENDING 3
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static u_char timer0_state;
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#ifdef PC98
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static u_char timer1_state;
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#endif
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static u_char timer2_state;
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static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
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#ifdef PC98
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static void rtc_serialcombit __P((int));
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static void rtc_serialcom __P((int));
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static int rtc_inb __P((void));
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static void rtc_outb __P((int));
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#endif
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static unsigned i8254_get_timecount __P((struct timecounter *tc));
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static unsigned tsc_get_timecount __P((struct timecounter *tc));
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static void set_timer_freq(u_int freq, int intr_freq);
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static struct timecounter tsc_timecounter = {
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tsc_get_timecount, /* get_timecount */
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0, /* no poll_pps */
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~0u, /* counter_mask */
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0, /* frequency */
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"TSC" /* name */
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};
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SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
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&tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
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static struct timecounter i8254_timecounter = {
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i8254_get_timecount, /* get_timecount */
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0, /* no poll_pps */
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~0u, /* counter_mask */
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0, /* frequency */
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"i8254" /* name */
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};
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SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
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&i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
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static void
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clkintr(struct clockframe frame)
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{
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if (timecounter->tc_get_timecount == i8254_get_timecount) {
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mtx_lock_spin(&clock_lock);
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if (i8254_ticked)
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i8254_ticked = 0;
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else {
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i8254_offset += timer0_max_count;
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i8254_lastcount = 0;
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}
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clkintr_pending = 0;
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mtx_unlock_spin(&clock_lock);
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}
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timer_func(&frame);
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#ifdef SMP
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if (timer_func == hardclock)
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forward_hardclock();
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#endif
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switch (timer0_state) {
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case RELEASED:
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break;
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case ACQUIRED:
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if ((timer0_prescaler_count += timer0_max_count)
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>= hardclock_max_count) {
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timer0_prescaler_count -= hardclock_max_count;
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hardclock(&frame);
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#ifdef SMP
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forward_hardclock();
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#endif
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}
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break;
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case ACQUIRE_PENDING:
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mtx_lock_spin(&clock_lock);
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i8254_offset = i8254_get_timecount(NULL);
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i8254_lastcount = 0;
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timer0_max_count = TIMER_DIV(new_rate);
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, timer0_max_count & 0xff);
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outb(TIMER_CNTR0, timer0_max_count >> 8);
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mtx_unlock_spin(&clock_lock);
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timer_func = new_function;
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timer0_state = ACQUIRED;
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break;
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case RELEASE_PENDING:
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if ((timer0_prescaler_count += timer0_max_count)
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>= hardclock_max_count) {
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mtx_lock_spin(&clock_lock);
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i8254_offset = i8254_get_timecount(NULL);
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i8254_lastcount = 0;
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timer0_max_count = hardclock_max_count;
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outb(TIMER_MODE,
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TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
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outb(TIMER_CNTR0, timer0_max_count & 0xff);
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outb(TIMER_CNTR0, timer0_max_count >> 8);
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mtx_unlock_spin(&clock_lock);
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timer0_prescaler_count = 0;
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timer_func = hardclock;
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timer0_state = RELEASED;
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hardclock(&frame);
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#ifdef SMP
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forward_hardclock();
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#endif
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}
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break;
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}
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#ifdef DEV_MCA
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/* Reset clock interrupt by asserting bit 7 of port 0x61 */
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if (MCA_system)
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outb(0x61, inb(0x61) | 0x80);
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#endif
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}
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/*
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* The acquire and release functions must be called at ipl >= splclock().
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*/
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int
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acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
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{
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static int old_rate;
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if (rate <= 0 || rate > TIMER0_MAX_FREQ)
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return (-1);
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switch (timer0_state) {
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case RELEASED:
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timer0_state = ACQUIRE_PENDING;
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break;
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case RELEASE_PENDING:
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if (rate != old_rate)
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return (-1);
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/*
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* The timer has been released recently, but is being
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* re-acquired before the release completed. In this
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* case, we simply reclaim it as if it had not been
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* released at all.
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*/
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timer0_state = ACQUIRED;
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break;
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default:
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return (-1); /* busy */
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}
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new_function = function;
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old_rate = new_rate = rate;
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return (0);
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}
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#ifdef PC98
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int
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acquire_timer1(int mode)
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{
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if (timer1_state != RELEASED)
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return (-1);
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timer1_state = ACQUIRED;
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/*
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* This access to the timer registers is as atomic as possible
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* because it is a single instruction. We could do better if we
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* knew the rate. Use of splclock() limits glitches to 10-100us,
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* and this is probably good enough for timer2, so we aren't as
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* careful with it as with timer0.
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*/
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outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f));
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return (0);
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}
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#endif
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int
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acquire_timer2(int mode)
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{
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if (timer2_state != RELEASED)
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return (-1);
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timer2_state = ACQUIRED;
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/*
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* This access to the timer registers is as atomic as possible
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* because it is a single instruction. We could do better if we
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* knew the rate. Use of splclock() limits glitches to 10-100us,
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* and this is probably good enough for timer2, so we aren't as
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* careful with it as with timer0.
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*/
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outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
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return (0);
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}
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int
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release_timer0()
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{
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switch (timer0_state) {
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case ACQUIRED:
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timer0_state = RELEASE_PENDING;
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break;
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case ACQUIRE_PENDING:
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/* Nothing happened yet, release quickly. */
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timer0_state = RELEASED;
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break;
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default:
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return (-1);
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}
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return (0);
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}
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#ifdef PC98
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int
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release_timer1()
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{
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if (timer1_state != ACQUIRED)
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return (-1);
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timer1_state = RELEASED;
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outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT);
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return (0);
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}
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#endif
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int
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release_timer2()
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{
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if (timer2_state != ACQUIRED)
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return (-1);
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timer2_state = RELEASED;
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outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
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return (0);
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}
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#ifndef PC98
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/*
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* This routine receives statistical clock interrupts from the RTC.
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* As explained above, these occur at 128 interrupts per second.
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* When profiling, we receive interrupts at a rate of 1024 Hz.
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*
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* This does not actually add as much overhead as it sounds, because
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* when the statistical clock is active, the hardclock driver no longer
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* needs to keep (inaccurate) statistics on its own. This decouples
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* statistics gathering from scheduling interrupts.
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*
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* The RTC chip requires that we read status register C (RTC_INTR)
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* to acknowledge an interrupt, before it will generate the next one.
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* Under high interrupt load, rtcintr() can be indefinitely delayed and
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* the clock can tick immediately after the read from RTC_INTR. In this
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* case, the mc146818A interrupt signal will not drop for long enough
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* to register with the 8259 PIC. If an interrupt is missed, the stat
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* clock will halt, considerably degrading system performance. This is
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* why we use 'while' rather than a more straightforward 'if' below.
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* Stat clock ticks can still be lost, causing minor loss of accuracy
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* in the statistics, but the stat clock will no longer stop.
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*/
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static void
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rtcintr(struct clockframe frame)
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{
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while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
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statclock(&frame);
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#ifdef SMP
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forward_statclock();
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#endif
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}
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}
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#include "opt_ddb.h"
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#ifdef DDB
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#include <ddb/ddb.h>
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DB_SHOW_COMMAND(rtc, rtc)
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{
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printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
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rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
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rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
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rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
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}
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#endif /* DDB */
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#endif /* for PC98 */
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static int
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getit(void)
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{
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int high, low;
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mtx_lock_spin(&clock_lock);
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/* Select timer0 and latch counter value. */
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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mtx_unlock_spin(&clock_lock);
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return ((high << 8) | low);
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}
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|
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/*
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* Wait "n" microseconds.
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* Relies on timer 1 counting down from (timer_freq / hz)
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* Note: timer had better have been programmed before this is first used!
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*/
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void
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DELAY(int n)
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{
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int delta, prev_tick, tick, ticks_left;
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#ifdef DELAYDEBUG
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int getit_calls = 1;
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int n1;
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static int state = 0;
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if (state == 0) {
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state = 1;
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for (n1 = 1; n1 <= 10000000; n1 *= 10)
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DELAY(n1);
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state = 2;
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}
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if (state == 1)
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printf("DELAY(%d)...", n);
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#endif
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/*
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* Guard against the timer being uninitialized if we are called
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* early for console i/o.
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*/
|
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if (timer0_max_count == 0)
|
|
set_timer_freq(timer_freq, hz);
|
|
|
|
/*
|
|
* Read the counter first, so that the rest of the setup overhead is
|
|
* counted. Guess the initial overhead is 20 usec (on most systems it
|
|
* takes about 1.5 usec for each of the i/o's in getit(). The loop
|
|
* takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
|
|
* multiplications and divisions to scale the count take a while).
|
|
*/
|
|
prev_tick = getit();
|
|
n -= 0; /* XXX actually guess no initial overhead */
|
|
/*
|
|
* Calculate (n * (timer_freq / 1e6)) without using floating point
|
|
* and without any avoidable overflows.
|
|
*/
|
|
if (n <= 0)
|
|
ticks_left = 0;
|
|
else if (n < 256)
|
|
/*
|
|
* Use fixed point to avoid a slow division by 1000000.
|
|
* 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
|
|
* 2^15 is the first power of 2 that gives exact results
|
|
* for n between 0 and 256.
|
|
*/
|
|
ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
|
|
else
|
|
/*
|
|
* Don't bother using fixed point, although gcc-2.7.2
|
|
* generates particularly poor code for the long long
|
|
* division, since even the slow way will complete long
|
|
* before the delay is up (unless we're interrupted).
|
|
*/
|
|
ticks_left = ((u_int)n * (long long)timer_freq + 999999)
|
|
/ 1000000;
|
|
|
|
while (ticks_left > 0) {
|
|
tick = getit();
|
|
#ifdef DELAYDEBUG
|
|
++getit_calls;
|
|
#endif
|
|
delta = prev_tick - tick;
|
|
prev_tick = tick;
|
|
if (delta < 0) {
|
|
delta += timer0_max_count;
|
|
/*
|
|
* Guard against timer0_max_count being wrong.
|
|
* This shouldn't happen in normal operation,
|
|
* but it may happen if set_timer_freq() is
|
|
* traced.
|
|
*/
|
|
if (delta < 0)
|
|
delta = 0;
|
|
}
|
|
ticks_left -= delta;
|
|
}
|
|
#ifdef DELAYDEBUG
|
|
if (state == 1)
|
|
printf(" %d calls to getit() at %d usec each\n",
|
|
getit_calls, (n + 5) / getit_calls);
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
sysbeepstop(void *chan)
|
|
{
|
|
#ifdef PC98 /* PC98 */
|
|
outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */
|
|
release_timer1();
|
|
#else
|
|
outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
|
|
release_timer2();
|
|
#endif
|
|
beeping = 0;
|
|
}
|
|
|
|
int
|
|
sysbeep(int pitch, int period)
|
|
{
|
|
int x = splclock();
|
|
|
|
#ifdef PC98
|
|
if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT))
|
|
if (!beeping) {
|
|
/* Something else owns it. */
|
|
splx(x);
|
|
return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
|
|
}
|
|
disable_intr();
|
|
outb(0x3fdb, pitch);
|
|
outb(0x3fdb, (pitch>>8));
|
|
enable_intr();
|
|
if (!beeping) {
|
|
/* enable counter1 output to speaker */
|
|
outb(IO_PPI, (inb(IO_PPI) & 0xf7));
|
|
beeping = period;
|
|
timeout(sysbeepstop, (void *)NULL, period);
|
|
}
|
|
#else
|
|
if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
|
|
if (!beeping) {
|
|
/* Something else owns it. */
|
|
splx(x);
|
|
return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
|
|
}
|
|
mtx_lock_spin(&clock_lock);
|
|
outb(TIMER_CNTR2, pitch);
|
|
outb(TIMER_CNTR2, (pitch>>8));
|
|
mtx_unlock_spin(&clock_lock);
|
|
if (!beeping) {
|
|
/* enable counter2 output to speaker */
|
|
outb(IO_PPI, inb(IO_PPI) | 3);
|
|
beeping = period;
|
|
timeout(sysbeepstop, (void *)NULL, period);
|
|
}
|
|
#endif
|
|
splx(x);
|
|
return (0);
|
|
}
|
|
|
|
#ifndef PC98
|
|
/*
|
|
* RTC support routines
|
|
*/
|
|
|
|
int
|
|
rtcin(reg)
|
|
int reg;
|
|
{
|
|
int s;
|
|
u_char val;
|
|
|
|
s = splhigh();
|
|
outb(IO_RTC, reg);
|
|
inb(0x84);
|
|
val = inb(IO_RTC + 1);
|
|
inb(0x84);
|
|
splx(s);
|
|
return (val);
|
|
}
|
|
|
|
static __inline void
|
|
writertc(u_char reg, u_char val)
|
|
{
|
|
int s;
|
|
|
|
s = splhigh();
|
|
inb(0x84);
|
|
outb(IO_RTC, reg);
|
|
inb(0x84);
|
|
outb(IO_RTC + 1, val);
|
|
inb(0x84); /* XXX work around wrong order in rtcin() */
|
|
splx(s);
|
|
}
|
|
|
|
static __inline int
|
|
readrtc(int port)
|
|
{
|
|
return(bcd2bin(rtcin(port)));
|
|
}
|
|
#endif
|
|
|
|
#ifdef PC98
|
|
unsigned int delaycount;
|
|
#define FIRST_GUESS 0x2000
|
|
static void findcpuspeed(void)
|
|
{
|
|
int i;
|
|
int remainder;
|
|
|
|
/* Put counter in count down mode */
|
|
outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN);
|
|
outb(TIMER_CNTR0, 0xff);
|
|
outb(TIMER_CNTR0, 0xff);
|
|
for (i = FIRST_GUESS; i; i--)
|
|
;
|
|
remainder = getit();
|
|
delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder);
|
|
}
|
|
#endif
|
|
|
|
#ifdef PC98
|
|
static u_int
|
|
calibrate_clocks(void)
|
|
{
|
|
int timeout;
|
|
u_int count, prev_count, tot_count;
|
|
u_short sec, start_sec;
|
|
|
|
if (bootverbose)
|
|
printf("Calibrating clock(s) ... ");
|
|
/* Check ARTIC. */
|
|
if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) &&
|
|
!(PC98_SYSTEM_PARAMETER(0x45b) & 0x04))
|
|
goto fail;
|
|
timeout = 100000000;
|
|
|
|
/* Read the ARTIC. */
|
|
sec = inw(0x5e);
|
|
|
|
/* Wait for the ARTIC to changes. */
|
|
start_sec = sec;
|
|
for (;;) {
|
|
sec = inw(0x5e);
|
|
if (sec != start_sec)
|
|
break;
|
|
if (--timeout == 0)
|
|
goto fail;
|
|
}
|
|
prev_count = getit();
|
|
if (prev_count == 0 || prev_count > timer0_max_count)
|
|
goto fail;
|
|
tot_count = 0;
|
|
|
|
if (tsc_present)
|
|
wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */
|
|
start_sec = sec;
|
|
for (;;) {
|
|
sec = inw(0x5e);
|
|
count = getit();
|
|
if (count == 0 || count > timer0_max_count)
|
|
goto fail;
|
|
if (count > prev_count)
|
|
tot_count += prev_count - (count - timer0_max_count);
|
|
else
|
|
tot_count += prev_count - count;
|
|
prev_count = count;
|
|
if ((sec == start_sec + 1200) ||
|
|
(sec < start_sec &&
|
|
(u_int)sec + 0x10000 == (u_int)start_sec + 1200))
|
|
break;
|
|
if (--timeout == 0)
|
|
goto fail;
|
|
}
|
|
/*
|
|
* Read the cpu cycle counter. The timing considerations are
|
|
* similar to those for the i8254 clock.
|
|
*/
|
|
if (tsc_present)
|
|
tsc_freq = rdtsc();
|
|
|
|
if (bootverbose) {
|
|
if (tsc_present)
|
|
printf("TSC clock: %u Hz, ", tsc_freq);
|
|
printf("i8254 clock: %u Hz\n", tot_count);
|
|
}
|
|
return (tot_count);
|
|
|
|
fail:
|
|
if (bootverbose)
|
|
printf("failed, using default i8254 clock of %u Hz\n",
|
|
timer_freq);
|
|
return (timer_freq);
|
|
}
|
|
#else
|
|
static u_int
|
|
calibrate_clocks(void)
|
|
{
|
|
u_int64_t old_tsc;
|
|
u_int count, prev_count, tot_count;
|
|
int sec, start_sec, timeout;
|
|
|
|
if (bootverbose)
|
|
printf("Calibrating clock(s) ... ");
|
|
if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
|
|
goto fail;
|
|
timeout = 100000000;
|
|
|
|
/* Read the mc146818A seconds counter. */
|
|
for (;;) {
|
|
if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
|
|
sec = rtcin(RTC_SEC);
|
|
break;
|
|
}
|
|
if (--timeout == 0)
|
|
goto fail;
|
|
}
|
|
|
|
/* Wait for the mC146818A seconds counter to change. */
|
|
start_sec = sec;
|
|
for (;;) {
|
|
if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
|
|
sec = rtcin(RTC_SEC);
|
|
if (sec != start_sec)
|
|
break;
|
|
}
|
|
if (--timeout == 0)
|
|
goto fail;
|
|
}
|
|
|
|
/* Start keeping track of the i8254 counter. */
|
|
prev_count = getit();
|
|
if (prev_count == 0 || prev_count > timer0_max_count)
|
|
goto fail;
|
|
tot_count = 0;
|
|
|
|
if (tsc_present)
|
|
old_tsc = rdtsc();
|
|
else
|
|
old_tsc = 0; /* shut up gcc */
|
|
|
|
/*
|
|
* Wait for the mc146818A seconds counter to change. Read the i8254
|
|
* counter for each iteration since this is convenient and only
|
|
* costs a few usec of inaccuracy. The timing of the final reads
|
|
* of the counters almost matches the timing of the initial reads,
|
|
* so the main cause of inaccuracy is the varying latency from
|
|
* inside getit() or rtcin(RTC_STATUSA) to the beginning of the
|
|
* rtcin(RTC_SEC) that returns a changed seconds count. The
|
|
* maximum inaccuracy from this cause is < 10 usec on 486's.
|
|
*/
|
|
start_sec = sec;
|
|
for (;;) {
|
|
if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
|
|
sec = rtcin(RTC_SEC);
|
|
count = getit();
|
|
if (count == 0 || count > timer0_max_count)
|
|
goto fail;
|
|
if (count > prev_count)
|
|
tot_count += prev_count - (count - timer0_max_count);
|
|
else
|
|
tot_count += prev_count - count;
|
|
prev_count = count;
|
|
if (sec != start_sec)
|
|
break;
|
|
if (--timeout == 0)
|
|
goto fail;
|
|
}
|
|
|
|
/*
|
|
* Read the cpu cycle counter. The timing considerations are
|
|
* similar to those for the i8254 clock.
|
|
*/
|
|
if (tsc_present)
|
|
tsc_freq = rdtsc() - old_tsc;
|
|
|
|
if (bootverbose) {
|
|
if (tsc_present)
|
|
printf("TSC clock: %u Hz, ", tsc_freq);
|
|
printf("i8254 clock: %u Hz\n", tot_count);
|
|
}
|
|
return (tot_count);
|
|
|
|
fail:
|
|
if (bootverbose)
|
|
printf("failed, using default i8254 clock of %u Hz\n",
|
|
timer_freq);
|
|
return (timer_freq);
|
|
}
|
|
#endif /* !PC98 */
|
|
|
|
static void
|
|
set_timer_freq(u_int freq, int intr_freq)
|
|
{
|
|
int new_timer0_max_count;
|
|
|
|
mtx_lock_spin(&clock_lock);
|
|
timer_freq = freq;
|
|
new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
|
|
if (new_timer0_max_count != timer0_max_count) {
|
|
timer0_max_count = new_timer0_max_count;
|
|
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
|
|
outb(TIMER_CNTR0, timer0_max_count & 0xff);
|
|
outb(TIMER_CNTR0, timer0_max_count >> 8);
|
|
}
|
|
mtx_unlock_spin(&clock_lock);
|
|
}
|
|
|
|
/*
|
|
* i8254_restore is called from apm_default_resume() to reload
|
|
* the countdown register.
|
|
* this should not be necessary but there are broken laptops that
|
|
* do not restore the countdown register on resume.
|
|
* when it happnes, it messes up the hardclock interval and system clock,
|
|
* which leads to the infamous "calcru: negative time" problem.
|
|
*/
|
|
static void
|
|
i8254_restore(void)
|
|
{
|
|
|
|
mtx_lock_spin(&clock_lock);
|
|
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
|
|
outb(TIMER_CNTR0, timer0_max_count & 0xff);
|
|
outb(TIMER_CNTR0, timer0_max_count >> 8);
|
|
mtx_unlock_spin(&clock_lock);
|
|
}
|
|
|
|
#ifndef PC98
|
|
static void
|
|
rtc_restore(void)
|
|
{
|
|
|
|
/* Reenable RTC updates and interrupts. */
|
|
/* XXX locking is needed for RTC access? */
|
|
writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
|
|
writertc(RTC_STATUSB, rtc_statusb);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Restore all the timers atomically.
|
|
*/
|
|
void
|
|
timer_restore(void)
|
|
{
|
|
|
|
i8254_restore(); /* restore timer_freq and hz */
|
|
#ifndef PC98
|
|
rtc_restore(); /* reenable RTC interrupts */
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Initialize 8254 timer 0 early so that it can be used in DELAY().
|
|
* XXX initialization of other timers is unintentionally left blank.
|
|
*/
|
|
void
|
|
startrtclock()
|
|
{
|
|
u_int delta, freq;
|
|
|
|
#ifdef PC98
|
|
findcpuspeed();
|
|
if (pc98_machine_type & M_8M)
|
|
timer_freq = 1996800L; /* 1.9968 MHz */
|
|
else
|
|
timer_freq = 2457600L; /* 2.4576 MHz */
|
|
#endif /* PC98 */
|
|
|
|
if (cpu_feature & CPUID_TSC)
|
|
tsc_present = 1;
|
|
else
|
|
tsc_present = 0;
|
|
|
|
#ifndef PC98
|
|
writertc(RTC_STATUSA, rtc_statusa);
|
|
writertc(RTC_STATUSB, RTCSB_24HR);
|
|
#endif
|
|
|
|
set_timer_freq(timer_freq, hz);
|
|
freq = calibrate_clocks();
|
|
#ifdef CLK_CALIBRATION_LOOP
|
|
if (bootverbose) {
|
|
printf(
|
|
"Press a key on the console to abort clock calibration\n");
|
|
while (cncheckc() == -1)
|
|
calibrate_clocks();
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Use the calibrated i8254 frequency if it seems reasonable.
|
|
* Otherwise use the default, and don't use the calibrated i586
|
|
* frequency.
|
|
*/
|
|
delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
|
|
if (delta < timer_freq / 100) {
|
|
#ifndef CLK_USE_I8254_CALIBRATION
|
|
if (bootverbose)
|
|
printf(
|
|
"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
|
|
freq = timer_freq;
|
|
#endif
|
|
timer_freq = freq;
|
|
} else {
|
|
if (bootverbose)
|
|
printf(
|
|
"%d Hz differs from default of %d Hz by more than 1%%\n",
|
|
freq, timer_freq);
|
|
tsc_freq = 0;
|
|
}
|
|
|
|
set_timer_freq(timer_freq, hz);
|
|
i8254_timecounter.tc_frequency = timer_freq;
|
|
tc_init(&i8254_timecounter);
|
|
|
|
#ifndef CLK_USE_TSC_CALIBRATION
|
|
if (tsc_freq != 0) {
|
|
if (bootverbose)
|
|
printf(
|
|
"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
|
|
tsc_freq = 0;
|
|
}
|
|
#endif
|
|
if (tsc_present && tsc_freq == 0) {
|
|
/*
|
|
* Calibration of the i586 clock relative to the mc146818A
|
|
* clock failed. Do a less accurate calibration relative
|
|
* to the i8254 clock.
|
|
*/
|
|
u_int64_t old_tsc = rdtsc();
|
|
|
|
DELAY(1000000);
|
|
tsc_freq = rdtsc() - old_tsc;
|
|
#ifdef CLK_USE_TSC_CALIBRATION
|
|
if (bootverbose)
|
|
printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
|
|
#endif
|
|
}
|
|
|
|
#if !defined(SMP)
|
|
/*
|
|
* We can not use the TSC in SMP mode, until we figure out a
|
|
* cheap (impossible), reliable and precise (yeah right!) way
|
|
* to synchronize the TSCs of all the CPUs.
|
|
* Curse Intel for leaving the counter out of the I/O APIC.
|
|
*/
|
|
|
|
/*
|
|
* We can not use the TSC if we support APM. Precise timekeeping
|
|
* on an APM'ed machine is at best a fools pursuit, since
|
|
* any and all of the time spent in various SMM code can't
|
|
* be reliably accounted for. Reading the RTC is your only
|
|
* source of reliable time info. The i8254 looses too of course
|
|
* but we need to have some kind of time...
|
|
* We don't know at this point whether APM is going to be used
|
|
* or not, nor when it might be activated. Play it safe.
|
|
*/
|
|
if (power_pm_get_type() == POWER_PM_TYPE_APM) {
|
|
if (bootverbose)
|
|
printf("TSC initialization skipped: APM enabled.\n");
|
|
return;
|
|
}
|
|
|
|
if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
|
|
tsc_timecounter.tc_frequency = tsc_freq;
|
|
tc_init(&tsc_timecounter);
|
|
}
|
|
|
|
#endif /* !defined(SMP) */
|
|
}
|
|
|
|
#ifdef PC98
|
|
static void
|
|
rtc_serialcombit(int i)
|
|
{
|
|
outb(IO_RTC, ((i&0x01)<<5)|0x07);
|
|
DELAY(1);
|
|
outb(IO_RTC, ((i&0x01)<<5)|0x17);
|
|
DELAY(1);
|
|
outb(IO_RTC, ((i&0x01)<<5)|0x07);
|
|
DELAY(1);
|
|
}
|
|
|
|
static void
|
|
rtc_serialcom(int i)
|
|
{
|
|
rtc_serialcombit(i&0x01);
|
|
rtc_serialcombit((i&0x02)>>1);
|
|
rtc_serialcombit((i&0x04)>>2);
|
|
rtc_serialcombit((i&0x08)>>3);
|
|
outb(IO_RTC, 0x07);
|
|
DELAY(1);
|
|
outb(IO_RTC, 0x0f);
|
|
DELAY(1);
|
|
outb(IO_RTC, 0x07);
|
|
DELAY(1);
|
|
}
|
|
|
|
static void
|
|
rtc_outb(int val)
|
|
{
|
|
int s;
|
|
int sa = 0;
|
|
|
|
for (s=0;s<8;s++) {
|
|
sa = ((val >> s) & 0x01) ? 0x27 : 0x07;
|
|
outb(IO_RTC, sa); /* set DI & CLK 0 */
|
|
DELAY(1);
|
|
outb(IO_RTC, sa | 0x10); /* CLK 1 */
|
|
DELAY(1);
|
|
}
|
|
outb(IO_RTC, sa & 0xef); /* CLK 0 */
|
|
}
|
|
|
|
static int
|
|
rtc_inb(void)
|
|
{
|
|
int s;
|
|
int sa = 0;
|
|
|
|
for (s=0;s<8;s++) {
|
|
sa |= ((inb(0x33) & 0x01) << s);
|
|
outb(IO_RTC, 0x17); /* CLK 1 */
|
|
DELAY(1);
|
|
outb(IO_RTC, 0x07); /* CLK 0 */
|
|
DELAY(2);
|
|
}
|
|
return sa;
|
|
}
|
|
#endif /* PC-98 */
|
|
|
|
/*
|
|
* Initialize the time of day register, based on the time base which is, e.g.
|
|
* from a filesystem.
|
|
*/
|
|
void
|
|
inittodr(time_t base)
|
|
{
|
|
unsigned long sec, days;
|
|
int year, month;
|
|
int y, m, s;
|
|
struct timespec ts;
|
|
#ifdef PC98
|
|
int second, min, hour;
|
|
#endif
|
|
|
|
if (base) {
|
|
s = splclock();
|
|
ts.tv_sec = base;
|
|
ts.tv_nsec = 0;
|
|
tc_setclock(&ts);
|
|
splx(s);
|
|
}
|
|
|
|
#ifdef PC98
|
|
rtc_serialcom(0x03); /* Time Read */
|
|
rtc_serialcom(0x01); /* Register shift command. */
|
|
DELAY(20);
|
|
|
|
second = bcd2bin(rtc_inb() & 0xff); /* sec */
|
|
min = bcd2bin(rtc_inb() & 0xff); /* min */
|
|
hour = bcd2bin(rtc_inb() & 0xff); /* hour */
|
|
days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */
|
|
|
|
month = (rtc_inb() >> 4) & 0x0f; /* month */
|
|
for (m = 1; m < month; m++)
|
|
days += daysinmonth[m-1];
|
|
year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */
|
|
/* 2000 year problem */
|
|
if (year < 1995)
|
|
year += 100;
|
|
if (year < 1970)
|
|
goto wrong_time;
|
|
for (y = 1970; y < year; y++)
|
|
days += DAYSPERYEAR + LEAPYEAR(y);
|
|
if ((month > 2) && LEAPYEAR(year))
|
|
days ++;
|
|
sec = ((( days * 24 +
|
|
hour) * 60 +
|
|
min) * 60 +
|
|
second);
|
|
/* sec now contains the number of seconds, since Jan 1 1970,
|
|
in the local time zone */
|
|
|
|
s = splhigh();
|
|
#else /* IBM-PC */
|
|
/* Look if we have a RTC present and the time is valid */
|
|
if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
|
|
goto wrong_time;
|
|
|
|
/* wait for time update to complete */
|
|
/* If RTCSA_TUP is zero, we have at least 244us before next update */
|
|
s = splhigh();
|
|
while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
|
|
splx(s);
|
|
s = splhigh();
|
|
}
|
|
|
|
days = 0;
|
|
#ifdef USE_RTC_CENTURY
|
|
year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
|
|
#else
|
|
year = readrtc(RTC_YEAR) + 1900;
|
|
if (year < 1970)
|
|
year += 100;
|
|
#endif
|
|
if (year < 1970) {
|
|
splx(s);
|
|
goto wrong_time;
|
|
}
|
|
month = readrtc(RTC_MONTH);
|
|
for (m = 1; m < month; m++)
|
|
days += daysinmonth[m-1];
|
|
if ((month > 2) && LEAPYEAR(year))
|
|
days ++;
|
|
days += readrtc(RTC_DAY) - 1;
|
|
for (y = 1970; y < year; y++)
|
|
days += DAYSPERYEAR + LEAPYEAR(y);
|
|
sec = ((( days * 24 +
|
|
readrtc(RTC_HRS)) * 60 +
|
|
readrtc(RTC_MIN)) * 60 +
|
|
readrtc(RTC_SEC));
|
|
/* sec now contains the number of seconds, since Jan 1 1970,
|
|
in the local time zone */
|
|
#endif
|
|
|
|
sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
|
|
|
|
y = time_second - sec;
|
|
if (y <= -2 || y >= 2) {
|
|
/* badly off, adjust it */
|
|
ts.tv_sec = sec;
|
|
ts.tv_nsec = 0;
|
|
tc_setclock(&ts);
|
|
}
|
|
splx(s);
|
|
return;
|
|
|
|
wrong_time:
|
|
printf("Invalid time in real time clock.\n");
|
|
printf("Check and reset the date immediately!\n");
|
|
}
|
|
|
|
/*
|
|
* Write system time back to RTC
|
|
*/
|
|
void
|
|
resettodr()
|
|
{
|
|
unsigned long tm;
|
|
int y, m, s;
|
|
#ifdef PC98
|
|
int wd;
|
|
#endif
|
|
|
|
if (disable_rtc_set)
|
|
return;
|
|
|
|
s = splclock();
|
|
tm = time_second;
|
|
splx(s);
|
|
|
|
#ifdef PC98
|
|
rtc_serialcom(0x01); /* Register shift command. */
|
|
|
|
/* Calculate local time to put in RTC */
|
|
|
|
tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
|
|
|
|
rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
|
|
rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
|
|
rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
|
|
|
|
/* We have now the days since 01-01-1970 in tm */
|
|
wd = (tm+4)%7;
|
|
for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
|
|
tm >= m;
|
|
y++, m = DAYSPERYEAR + LEAPYEAR(y))
|
|
tm -= m;
|
|
|
|
/* Now we have the years in y and the day-of-the-year in tm */
|
|
for (m = 0; ; m++) {
|
|
int ml;
|
|
|
|
ml = daysinmonth[m];
|
|
if (m == 1 && LEAPYEAR(y))
|
|
ml++;
|
|
if (tm < ml)
|
|
break;
|
|
tm -= ml;
|
|
}
|
|
|
|
m++;
|
|
rtc_outb(bin2bcd(tm+1)); /* Write back Day */
|
|
rtc_outb((m << 4) | wd); /* Write back Month & Weekday */
|
|
rtc_outb(bin2bcd(y%100)); /* Write back Year */
|
|
|
|
rtc_serialcom(0x02); /* Time set & Counter hold command. */
|
|
rtc_serialcom(0x00); /* Register hold command. */
|
|
#else
|
|
/* Disable RTC updates and interrupts. */
|
|
writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
|
|
|
|
/* Calculate local time to put in RTC */
|
|
|
|
tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
|
|
|
|
writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
|
|
writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
|
|
writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
|
|
|
|
/* We have now the days since 01-01-1970 in tm */
|
|
writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
|
|
for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
|
|
tm >= m;
|
|
y++, m = DAYSPERYEAR + LEAPYEAR(y))
|
|
tm -= m;
|
|
|
|
/* Now we have the years in y and the day-of-the-year in tm */
|
|
writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
|
|
#ifdef USE_RTC_CENTURY
|
|
writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
|
|
#endif
|
|
for (m = 0; ; m++) {
|
|
int ml;
|
|
|
|
ml = daysinmonth[m];
|
|
if (m == 1 && LEAPYEAR(y))
|
|
ml++;
|
|
if (tm < ml)
|
|
break;
|
|
tm -= ml;
|
|
}
|
|
|
|
writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
|
|
writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
|
|
|
|
/* Reenable RTC updates and interrupts. */
|
|
writertc(RTC_STATUSB, rtc_statusb);
|
|
#endif /* PC98 */
|
|
}
|
|
|
|
|
|
/*
|
|
* Start both clocks running.
|
|
*/
|
|
void
|
|
cpu_initclocks()
|
|
{
|
|
#ifndef PC98
|
|
int diag;
|
|
#endif
|
|
#ifdef APIC_IO
|
|
int apic_8254_trial;
|
|
void *clkdesc;
|
|
#endif /* APIC_IO */
|
|
|
|
#ifndef PC98
|
|
if (statclock_disable) {
|
|
/*
|
|
* The stat interrupt mask is different without the
|
|
* statistics clock. Also, don't set the interrupt
|
|
* flag which would normally cause the RTC to generate
|
|
* interrupts.
|
|
*/
|
|
rtc_statusb = RTCSB_24HR;
|
|
} else {
|
|
/* Setting stathz to nonzero early helps avoid races. */
|
|
stathz = RTC_NOPROFRATE;
|
|
profhz = RTC_PROFRATE;
|
|
}
|
|
#endif
|
|
|
|
/* Finish initializing 8253 timer 0. */
|
|
#ifdef APIC_IO
|
|
|
|
apic_8254_intr = isa_apic_irq(0);
|
|
apic_8254_trial = 0;
|
|
if (apic_8254_intr >= 0 ) {
|
|
if (apic_int_type(0, 0) == 3)
|
|
apic_8254_trial = 1;
|
|
} else {
|
|
/* look for ExtInt on pin 0 */
|
|
if (apic_int_type(0, 0) == 3) {
|
|
apic_8254_intr = apic_irq(0, 0);
|
|
setup_8254_mixed_mode();
|
|
} else
|
|
panic("APIC_IO: Cannot route 8254 interrupt to CPU");
|
|
}
|
|
|
|
inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL,
|
|
INTR_TYPE_CLK | INTR_FAST, &clkdesc);
|
|
mtx_lock_spin(&icu_lock);
|
|
INTREN(1 << apic_8254_intr);
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
#else /* APIC_IO */
|
|
|
|
/*
|
|
* XXX Check the priority of this interrupt handler. I
|
|
* couldn't find anything suitable in the BSD/OS code (grog,
|
|
* 19 July 2000).
|
|
*/
|
|
inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL,
|
|
INTR_TYPE_CLK | INTR_FAST, NULL);
|
|
mtx_lock_spin(&icu_lock);
|
|
INTREN(IRQ0);
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
#endif /* APIC_IO */
|
|
|
|
#ifndef PC98
|
|
/* Initialize RTC. */
|
|
writertc(RTC_STATUSA, rtc_statusa);
|
|
writertc(RTC_STATUSB, RTCSB_24HR);
|
|
|
|
/* Don't bother enabling the statistics clock. */
|
|
if (statclock_disable)
|
|
return;
|
|
diag = rtcin(RTC_DIAG);
|
|
if (diag != 0)
|
|
printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
|
|
#endif /* !PC98 */
|
|
|
|
#ifndef PC98
|
|
#ifdef APIC_IO
|
|
if (isa_apic_irq(8) != 8)
|
|
panic("APIC RTC != 8");
|
|
#endif /* APIC_IO */
|
|
|
|
inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL,
|
|
INTR_TYPE_CLK | INTR_FAST, NULL);
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
#ifdef APIC_IO
|
|
INTREN(APIC_IRQ8);
|
|
#else
|
|
INTREN(IRQ8);
|
|
#endif /* APIC_IO */
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
writertc(RTC_STATUSB, rtc_statusb);
|
|
#endif /* PC98 */
|
|
|
|
#ifdef APIC_IO
|
|
if (apic_8254_trial) {
|
|
|
|
printf("APIC_IO: Testing 8254 interrupt delivery\n");
|
|
while (read_intr_count(8) < 6)
|
|
; /* nothing */
|
|
if (read_intr_count(apic_8254_intr) < 3) {
|
|
/*
|
|
* The MP table is broken.
|
|
* The 8254 was not connected to the specified pin
|
|
* on the IO APIC.
|
|
* Workaround: Limited variant of mixed mode.
|
|
*/
|
|
mtx_lock_spin(&icu_lock);
|
|
INTRDIS(1 << apic_8254_intr);
|
|
mtx_unlock_spin(&icu_lock);
|
|
inthand_remove(clkdesc);
|
|
printf("APIC_IO: Broken MP table detected: "
|
|
"8254 is not connected to "
|
|
"IOAPIC #%d intpin %d\n",
|
|
int_to_apicintpin[apic_8254_intr].ioapic,
|
|
int_to_apicintpin[apic_8254_intr].int_pin);
|
|
/*
|
|
* Revoke current ISA IRQ 0 assignment and
|
|
* configure a fallback interrupt routing from
|
|
* the 8254 Timer via the 8259 PIC to the
|
|
* an ExtInt interrupt line on IOAPIC #0 intpin 0.
|
|
* We reuse the low level interrupt handler number.
|
|
*/
|
|
if (apic_irq(0, 0) < 0) {
|
|
revoke_apic_irq(apic_8254_intr);
|
|
assign_apic_irq(0, 0, apic_8254_intr);
|
|
}
|
|
apic_8254_intr = apic_irq(0, 0);
|
|
setup_8254_mixed_mode();
|
|
inthand_add("clk", apic_8254_intr,
|
|
(driver_intr_t *)clkintr, NULL,
|
|
INTR_TYPE_CLK | INTR_FAST, NULL);
|
|
mtx_lock_spin(&icu_lock);
|
|
INTREN(1 << apic_8254_intr);
|
|
mtx_unlock_spin(&icu_lock);
|
|
}
|
|
|
|
}
|
|
if (apic_int_type(0, 0) != 3 ||
|
|
int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
|
|
int_to_apicintpin[apic_8254_intr].int_pin != 0)
|
|
printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
|
|
int_to_apicintpin[apic_8254_intr].ioapic,
|
|
int_to_apicintpin[apic_8254_intr].int_pin);
|
|
else
|
|
printf("APIC_IO: "
|
|
"routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
|
|
#endif
|
|
|
|
}
|
|
|
|
#ifdef APIC_IO
|
|
static u_long
|
|
read_intr_count(int vec)
|
|
{
|
|
u_long *up;
|
|
up = intr_countp[vec];
|
|
if (up)
|
|
return *up;
|
|
return 0UL;
|
|
}
|
|
|
|
static void
|
|
setup_8254_mixed_mode()
|
|
{
|
|
/*
|
|
* Allow 8254 timer to INTerrupt 8259:
|
|
* re-initialize master 8259:
|
|
* reset; prog 4 bytes, single ICU, edge triggered
|
|
*/
|
|
outb(IO_ICU1, 0x13);
|
|
#ifdef PC98
|
|
outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */
|
|
outb(IO_ICU1 + 2, 0x00); /* ignore slave */
|
|
outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */
|
|
outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */
|
|
#else
|
|
outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
|
|
outb(IO_ICU1 + 1, 0x00); /* ignore slave */
|
|
outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
|
|
outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
|
|
#endif
|
|
|
|
/* program IO APIC for type 3 INT on INT0 */
|
|
if (ext_int_setup(0, 0) < 0)
|
|
panic("8254 redirect via APIC pin0 impossible!");
|
|
}
|
|
#endif
|
|
|
|
void
|
|
setstatclockrate(int newhz)
|
|
{
|
|
#ifndef PC98
|
|
if (newhz == RTC_PROFRATE)
|
|
rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
|
|
else
|
|
rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
|
|
writertc(RTC_STATUSA, rtc_statusa);
|
|
#endif
|
|
}
|
|
|
|
static int
|
|
sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
int error;
|
|
u_int freq;
|
|
|
|
/*
|
|
* Use `i8254' instead of `timer' in external names because `timer'
|
|
* is is too generic. Should use it everywhere.
|
|
*/
|
|
freq = timer_freq;
|
|
error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
|
|
if (error == 0 && req->newptr != NULL) {
|
|
if (timer0_state != RELEASED)
|
|
return (EBUSY); /* too much trouble to handle */
|
|
set_timer_freq(freq, hz);
|
|
i8254_timecounter.tc_frequency = freq;
|
|
tc_update(&i8254_timecounter);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
|
|
0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", "");
|
|
|
|
static int
|
|
sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
int error;
|
|
u_int freq;
|
|
|
|
if (tsc_timecounter.tc_frequency == 0)
|
|
return (EOPNOTSUPP);
|
|
freq = tsc_freq;
|
|
error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
|
|
if (error == 0 && req->newptr != NULL) {
|
|
tsc_freq = freq;
|
|
tsc_timecounter.tc_frequency = tsc_freq;
|
|
tc_update(&tsc_timecounter);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
|
|
0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", "");
|
|
|
|
static unsigned
|
|
i8254_get_timecount(struct timecounter *tc)
|
|
{
|
|
u_int count;
|
|
u_int high, low;
|
|
u_int eflags;
|
|
|
|
eflags = read_eflags();
|
|
mtx_lock_spin(&clock_lock);
|
|
|
|
/* Select timer0 and latch counter value. */
|
|
outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
|
|
|
|
low = inb(TIMER_CNTR0);
|
|
high = inb(TIMER_CNTR0);
|
|
count = timer0_max_count - ((high << 8) | low);
|
|
if (count < i8254_lastcount ||
|
|
(!i8254_ticked && (clkintr_pending ||
|
|
((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
|
|
#ifdef APIC_IO
|
|
#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
|
|
/* XXX this assumes that apic_8254_intr is < 24. */
|
|
(lapic_irr1 & (1 << apic_8254_intr))))
|
|
#else
|
|
(inb(IO_ICU1) & 1)))
|
|
#endif
|
|
)) {
|
|
i8254_ticked = 1;
|
|
i8254_offset += timer0_max_count;
|
|
}
|
|
i8254_lastcount = count;
|
|
count += i8254_offset;
|
|
mtx_unlock_spin(&clock_lock);
|
|
return (count);
|
|
}
|
|
|
|
static unsigned
|
|
tsc_get_timecount(struct timecounter *tc)
|
|
{
|
|
return (rdtsc());
|
|
}
|
|
|
|
#ifdef DEV_ISA
|
|
/*
|
|
* Attach to the ISA PnP descriptors for the timer and realtime clock.
|
|
*/
|
|
static struct isa_pnp_id attimer_ids[] = {
|
|
{ 0x0001d041 /* PNP0100 */, "AT timer" },
|
|
{ 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
|
|
{ 0 }
|
|
};
|
|
|
|
static int
|
|
attimer_probe(device_t dev)
|
|
{
|
|
int result;
|
|
|
|
if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
|
|
device_quiet(dev);
|
|
return(result);
|
|
}
|
|
|
|
static int
|
|
attimer_attach(device_t dev)
|
|
{
|
|
return(0);
|
|
}
|
|
|
|
static device_method_t attimer_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, attimer_probe),
|
|
DEVMETHOD(device_attach, attimer_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
|
|
DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t attimer_driver = {
|
|
"attimer",
|
|
attimer_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t attimer_devclass;
|
|
|
|
DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
|
|
#ifndef PC98
|
|
DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);
|
|
#endif
|
|
#endif /* DEV_ISA */
|