c7ecc129d7
ISDN4BSD is the work of our brand-new comitter: Hellmuth Michaelis, who has done a tremendous amount of work to bring us this far. There are still some outstanding issues and files to bring into the tree, and for now it will be needed to pick up all the extra docs from the isdn4bsd release. It is probably also a very good idea to subscribe to the isdn@freebsd.org mailing list before you try this out. These files correspond to release "beta Version 0.70.00 / December 1998" from Hellmuth.
441 lines
12 KiB
C
441 lines
12 KiB
C
/*
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* Copyright (c) 1997, 1998 Hellmuth Michaelis. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* i4b_usr_sti.c - USRobotics Sportster ISDN TA intern (Tina-pp)
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* -------------------------------------------------------------
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*
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* $Id: i4b_usr_sti.c,v 1.16 1998/12/05 18:05:02 hm Exp $
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*
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* last edit-date: [Sat Dec 5 18:25:34 1998]
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*
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*---------------------------------------------------------------------------*/
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#if defined(__FreeBSD__)
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#include "isic.h"
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#include "opt_i4b.h"
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#else
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#define NISIC 1
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#endif
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#if NISIC > 0 && defined(USR_STI)
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#include <sys/param.h>
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#if defined(__FreeBSD__) && __FreeBSD__ >= 3
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#include <sys/ioccom.h>
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#else
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#include <sys/ioctl.h>
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#endif
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#ifdef __FreeBSD__
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#include <machine/clock.h>
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#include <i386/isa/isa_device.h>
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#else
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#include <machine/bus.h>
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#include <sys/device.h>
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#endif
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#include <sys/socket.h>
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#include <net/if.h>
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#ifdef __FreeBSD__
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#include <machine/i4b_debug.h>
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#include <machine/i4b_ioctl.h>
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#else
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#include <i4b/i4b_debug.h>
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#include <i4b/i4b_ioctl.h>
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#endif
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#include <i4b/layer1/i4b_l1.h>
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#include <i4b/layer1/i4b_isac.h>
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#include <i4b/layer1/i4b_hscx.h>
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#include <i4b/include/i4b_global.h>
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/*---------------------------------------------------------------------------*
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* USR Sportster TA intern special registers
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*---------------------------------------------------------------------------*/
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#define USR_HSCXA_OFF 0x0000
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#define USR_HSCXB_OFF 0x4000
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#define USR_INTL_OFF 0x8000
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#define USR_ISAC_OFF 0xc000
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#define USR_RES_BIT 0x80 /* 0 = normal, 1 = reset ISAC/HSCX */
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#define USR_INTE_BIT 0x40 /* 0 = IRQ disabled, 1 = IRQ's enabled */
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#define USR_IL_MASK 0x07 /* IRQ level config */
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static u_char intr_no[] = { 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 3, 4, 5, 0, 6, 7 };
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#ifdef __FreeBSD__
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#define ADDR(reg) \
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(((reg/4) * 1024) + ((reg%4) * 2))
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/*---------------------------------------------------------------------------*
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* USRobotics read fifo routine
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*---------------------------------------------------------------------------*/
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static void
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usrtai_read_fifo(void *buf, const void *base, size_t len)
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{
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register int offset = 0;
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for(;len > 0; len--, offset++)
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*((u_char *)buf + offset) = inb((int)base + ADDR(offset));
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}
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/*---------------------------------------------------------------------------*
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* USRobotics write fifo routine
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*---------------------------------------------------------------------------*/
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static void
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usrtai_write_fifo(void *base, const void *buf, size_t len)
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{
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register int offset = 0;
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for(;len > 0; len--, offset++)
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outb((int)base + ADDR(offset), *((u_char *)buf + offset));
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}
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/*---------------------------------------------------------------------------*
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* USRobotics write register routine
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*---------------------------------------------------------------------------*/
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static void
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usrtai_write_reg(u_char *base, u_int offset, u_int v)
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{
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outb((int)base + ADDR(offset), (u_char)v);
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}
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/*---------------------------------------------------------------------------*
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* USRobotics read register routine
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*---------------------------------------------------------------------------*/
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static u_char
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usrtai_read_reg(u_char *base, u_int offset)
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{
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return(inb((int)base + ADDR(offset)));
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}
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/*---------------------------------------------------------------------------*
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* isic_probe_usrtai - probe for USR
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*---------------------------------------------------------------------------*/
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int
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isic_probe_usrtai(struct isa_device *dev)
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{
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struct isic_softc *sc = &isic_sc[dev->id_unit];
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/* check max unit range */
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if(dev->id_unit >= ISIC_MAXUNIT)
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{
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printf("isic%d: Error, unit %d >= MAXUNIT for USR Sportster TA!\n",
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dev->id_unit, dev->id_unit);
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return(0);
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}
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sc->sc_unit = dev->id_unit;
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/* check IRQ validity */
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if((intr_no[ffs(dev->id_irq) - 1]) == 0)
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{
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printf("isic%d: Error, invalid IRQ [%d] specified for USR Sportster TA!\n",
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dev->id_unit, (ffs(dev->id_irq))-1);
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return(0);
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}
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sc->sc_irq = dev->id_irq;
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/* check if memory addr specified */
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if(dev->id_maddr)
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{
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printf("isic%d: Error, mem addr 0x%lx specified for USR Sportster TA!\n",
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dev->id_unit, (u_long)dev->id_maddr);
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return(0);
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}
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dev->id_msize = 0;
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/* check if we got an iobase */
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switch(dev->id_iobase)
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{
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case 0x200:
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case 0x208:
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case 0x210:
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case 0x218:
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case 0x220:
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case 0x228:
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case 0x230:
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case 0x238:
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case 0x240:
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case 0x248:
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case 0x250:
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case 0x258:
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case 0x260:
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case 0x268:
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case 0x270:
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case 0x278:
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break;
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default:
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printf("isic%d: Error, invalid iobase 0x%x specified for USR Sportster TA!\n",
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dev->id_unit, dev->id_iobase);
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return(0);
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break;
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}
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sc->sc_port = dev->id_iobase;
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/* setup ISAC access routines */
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sc->clearirq = NULL;
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sc->readreg = usrtai_read_reg;
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sc->writereg = usrtai_write_reg;
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sc->readfifo = usrtai_read_fifo;
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sc->writefifo = usrtai_write_fifo;
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/* setup card type */
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sc->sc_cardtyp = CARD_TYPEP_USRTA;
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/* setup IOM bus type */
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sc->sc_bustyp = BUS_TYPE_IOM2;
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sc->sc_ipac = 0;
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sc->sc_bfifolen = HSCX_FIFO_LEN;
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/* setup ISAC and HSCX base addr */
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ISAC_BASE = (caddr_t)dev->id_iobase + USR_ISAC_OFF;
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HSCX_A_BASE = (caddr_t)dev->id_iobase + USR_HSCXA_OFF;
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HSCX_B_BASE = (caddr_t)dev->id_iobase + USR_HSCXB_OFF;
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/*
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* Read HSCX A/B VSTR. Expected value for USR Sportster TA based
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* boards is 0x05 in the least significant bits.
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*/
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if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
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((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
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{
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printf("isic%d: HSCX VSTR test failed for USR Sportster TA\n",
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dev->id_unit);
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printf("isic%d: HSC0: VSTR: %#x\n",
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dev->id_unit, HSCX_READ(0, H_VSTR));
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printf("isic%d: HSC1: VSTR: %#x\n",
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dev->id_unit, HSCX_READ(1, H_VSTR));
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return (0);
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}
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return (1);
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}
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/*---------------------------------------------------------------------------*
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* isic_attach_usrtai - attach USR
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*---------------------------------------------------------------------------*/
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int
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isic_attach_usrtai(struct isa_device *dev)
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{
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u_char irq = 0;
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/* reset the HSCX and ISAC chips */
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outb(dev->id_iobase + USR_INTL_OFF, USR_RES_BIT);
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DELAY(SEC_DELAY / 10);
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outb(dev->id_iobase + USR_INTL_OFF, 0x00);
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DELAY(SEC_DELAY / 10);
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/* setup IRQ */
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if((irq = intr_no[ffs(dev->id_irq) - 1]) == 0)
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{
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printf("isic%d: Attach error, invalid IRQ [%d] specified for USR Sportster TA!\n",
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dev->id_unit, ffs(dev->id_irq)-1);
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return(0);
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}
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/* configure and enable irq */
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outb(dev->id_iobase + USR_INTL_OFF, irq | USR_INTE_BIT);
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DELAY(SEC_DELAY / 10);
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return (1);
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}
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#else /* end of FreeBSD, start NetBSD */
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/*
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* Use of sc->sc_maps:
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* 0 : config register
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* 1 - 16 : HSCX A registers
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* 17 - 32 : HSCX B registers
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* 33 - 48 : ISAC registers
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*/
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#define USR_REG_OFFS(reg) ((reg % 4) * 2)
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#define USR_HSCXA_MAP(reg) ((reg / 4) + 1)
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#define USR_HSCXB_MAP(reg) ((reg / 4) + 17)
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#define USR_ISAC_MAP(reg) ((reg / 4) + 33)
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static int map_base[] = { 33, 1, 17, 0 }; /* ISAC, HSCX A, HSCX B */
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/*---------------------------------------------------------------------------*
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* USRobotics read fifo routine
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*---------------------------------------------------------------------------*/
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static void
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usrtai_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size)
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{
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int map, off, offset;
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u_char * p = buf;
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bus_space_tag_t t;
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bus_space_handle_t h;
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for (offset = 0; size > 0; size--, offset++) {
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map = map_base[what] + (offset / 4);
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t = sc->sc_maps[map].t;
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h = sc->sc_maps[map].h;
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off = USR_REG_OFFS(offset);
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*p++ = bus_space_read_1(t, h, off);
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}
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}
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/*---------------------------------------------------------------------------*
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* USRobotics write fifo routine
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*---------------------------------------------------------------------------*/
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static void
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usrtai_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
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{
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int map, off, offset;
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const u_char * p = buf;
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bus_space_tag_t t;
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bus_space_handle_t h;
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u_char v;
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for (offset = 0; size > 0; size--, offset++) {
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map = map_base[what] + (offset / 4);
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t = sc->sc_maps[map].t;
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h = sc->sc_maps[map].h;
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off = USR_REG_OFFS(offset);
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v = *p++;
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bus_space_write_1(t, h, off, v);
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}
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}
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/*---------------------------------------------------------------------------*
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* USRobotics write register routine
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*---------------------------------------------------------------------------*/
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static void
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usrtai_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data)
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{
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int map = map_base[what] + (offs / 4),
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off = USR_REG_OFFS(offs);
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bus_space_tag_t t = sc->sc_maps[map].t;
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bus_space_handle_t h = sc->sc_maps[map].h;
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bus_space_write_1(t, h, off, data);
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}
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/*---------------------------------------------------------------------------*
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* USRobotics read register routine
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*---------------------------------------------------------------------------*/
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static u_char
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usrtai_read_reg(struct isic_softc *sc, int what, bus_size_t offs)
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{
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int map = map_base[what] + (offs / 4),
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off = USR_REG_OFFS(offs);
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bus_space_tag_t t = sc->sc_maps[map].t;
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bus_space_handle_t h = sc->sc_maps[map].h;
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return bus_space_read_1(t, h, off);
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}
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/*---------------------------------------------------------------------------*
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* isic_probe_usrtai - probe for USR
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*---------------------------------------------------------------------------*/
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int
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isic_probe_usrtai(struct isic_attach_args *ia)
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{
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/*
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* Read HSCX A/B VSTR. Expected value for IOM2 based
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* boards is 0x05 in the least significant bits.
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*/
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if(((bus_space_read_1(ia->ia_maps[USR_HSCXA_MAP(H_VSTR)].t, ia->ia_maps[USR_HSCXA_MAP(H_VSTR)].h, USR_REG_OFFS(H_VSTR)) & 0x0f) != 0x05) ||
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((bus_space_read_1(ia->ia_maps[USR_HSCXB_MAP(H_VSTR)].t, ia->ia_maps[USR_HSCXB_MAP(H_VSTR)].h, USR_REG_OFFS(H_VSTR)) & 0x0f) != 0x05))
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return 0;
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return (1);
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}
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/*---------------------------------------------------------------------------*
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* isic_attach_usrtai - attach USR
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*---------------------------------------------------------------------------*/
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int
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isic_attach_usrtai(struct isic_softc *sc)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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u_char irq = intr_no[sc->sc_irq];
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sc->clearirq = NULL;
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sc->readreg = usrtai_read_reg;
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sc->writereg = usrtai_write_reg;
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sc->readfifo = usrtai_read_fifo;
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sc->writefifo = usrtai_write_fifo;
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/* setup card type */
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sc->sc_cardtyp = CARD_TYPEP_USRTA;
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/* setup IOM bus type */
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sc->sc_bustyp = BUS_TYPE_IOM2;
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sc->sc_ipac = 0;
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sc->sc_bfifolen = HSCX_FIFO_LEN;
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/* reset the HSCX and ISAC chips */
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bus_space_write_1(t, h, 0, USR_RES_BIT);
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DELAY(SEC_DELAY / 10);
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bus_space_write_1(t, h, 0, 0x00);
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DELAY(SEC_DELAY / 10);
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/* setup IRQ */
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bus_space_write_1(t, h, 0, irq | USR_INTE_BIT);
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DELAY(SEC_DELAY / 10);
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return (1);
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}
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#endif /* __FreeBSD__ */
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#endif /* ISIC > 0 */
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