5a10a1e2e6
Chelsio's TCP offload engine supports direct DMA of received TCP payload into wired user buffers. This feature is known as Direct-Data Placement. However, to scale well the adapter needs to prepare buffers for DDP before data arrives. aio_read() is more amenable to this requirement than read() as applications often call read() only after data is available in the socket buffer. When DDP is enabled, TOE sockets use the recently added pru_aio_queue protocol hook to claim aio_read(2) requests instead of letting them use the default AIO socket logic. The DDP feature supports scheduling DMA to two buffers at a time so that the second buffer is ready for use after the first buffer is filled. The aio/DDP code optimizes the case of an application ping-ponging between two buffers (similar to the zero-copy bpf(4) code) by keeping the two most recently used AIO buffers wired. If a buffer is reused, the aio/DDP code is able to reuse the vm_page_t array as well as page pod mappings (a kind of MMU mapping the Chelsio NIC uses to describe user buffers). The generation of the vmspace of the calling process is used in conjunction with the user buffer's address and length to determine if a user buffer matches a previously used buffer. If an application queues a buffer for AIO that does not match a previously used buffer then the least recently used buffer is unwired before the new buffer is wired. This ensures that no more than two user buffers per socket are ever wired. Note that this feature is best suited to applications sending a steady stream of data vs short bursts of traffic. Discussed with: np Relnotes: yes Sponsored by: Chelsio Communications
161 lines
4.4 KiB
C
161 lines
4.4 KiB
C
/*-
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* Copyright (c) 2010 Chelsio Communications, Inc.
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* All rights reserved.
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* Written by: Navdeep Parhar <np@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __T4_OFFLOAD_H__
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#define __T4_OFFLOAD_H__
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#define INIT_ULPTX_WRH(w, wrlen, atomic, tid) do { \
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(w)->wr_hi = htonl(V_FW_WR_OP(FW_ULPTX_WR) | V_FW_WR_ATOMIC(atomic)); \
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(w)->wr_mid = htonl(V_FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \
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V_FW_WR_FLOWID(tid)); \
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(w)->wr_lo = cpu_to_be64(0); \
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} while (0)
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#define INIT_ULPTX_WR(w, wrlen, atomic, tid) \
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INIT_ULPTX_WRH(&((w)->wr), wrlen, atomic, tid)
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#define INIT_TP_WR(w, tid) do { \
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(w)->wr.wr_hi = htonl(V_FW_WR_OP(FW_TP_WR) | \
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V_FW_WR_IMMDLEN(sizeof(*w) - sizeof(w->wr))); \
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(w)->wr.wr_mid = htonl(V_FW_WR_LEN16(DIV_ROUND_UP(sizeof(*w), 16)) | \
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V_FW_WR_FLOWID(tid)); \
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(w)->wr.wr_lo = cpu_to_be64(0); \
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} while (0)
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#define INIT_TP_WR_MIT_CPL(w, cpl, tid) do { \
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INIT_TP_WR(w, tid); \
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OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \
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} while (0)
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TAILQ_HEAD(stid_head, stid_region);
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struct listen_ctx;
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struct stid_region {
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TAILQ_ENTRY(stid_region) link;
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u_int used; /* # of stids used by this region */
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u_int free; /* # of contiguous stids free right after this region */
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};
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/*
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* Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
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*/
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#define MAX_ATIDS 8192U
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union aopen_entry {
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void *data;
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union aopen_entry *next;
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};
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/*
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* Holds the size, base address, free list start, etc of the TID, server TID,
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* and active-open TID tables. The tables themselves are allocated dynamically.
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*/
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struct tid_info {
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void **tid_tab;
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u_int ntids;
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u_int tids_in_use;
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struct mtx stid_lock __aligned(CACHE_LINE_SIZE);
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struct listen_ctx **stid_tab;
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u_int nstids;
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u_int stid_base;
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u_int stids_in_use;
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u_int nstids_free_head; /* # of available stids at the beginning */
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struct stid_head stids;
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struct mtx atid_lock __aligned(CACHE_LINE_SIZE);
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union aopen_entry *atid_tab;
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u_int natids;
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union aopen_entry *afree;
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u_int atids_in_use;
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struct mtx ftid_lock __aligned(CACHE_LINE_SIZE);
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struct filter_entry *ftid_tab;
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u_int nftids;
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u_int ftid_base;
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u_int ftids_in_use;
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struct mtx etid_lock __aligned(CACHE_LINE_SIZE);
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struct etid_entry *etid_tab;
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u_int netids;
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u_int etid_base;
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};
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struct t4_range {
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u_int start;
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u_int size;
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};
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struct t4_virt_res { /* virtualized HW resources */
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struct t4_range ddp;
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struct t4_range iscsi;
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struct t4_range stag;
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struct t4_range rq;
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struct t4_range pbl;
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struct t4_range qp;
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struct t4_range cq;
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struct t4_range ocq;
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struct t4_range l2t;
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};
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enum {
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ULD_TOM = 0,
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ULD_IWARP,
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ULD_ISCSI,
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ULD_MAX = ULD_ISCSI
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};
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struct adapter;
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struct port_info;
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struct uld_info {
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SLIST_ENTRY(uld_info) link;
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int refcount;
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int uld_id;
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int (*activate)(struct adapter *);
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int (*deactivate)(struct adapter *);
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};
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struct tom_tunables {
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int sndbuf;
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int ddp;
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int rx_coalesce;
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int tx_align;
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};
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#ifdef TCP_OFFLOAD
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int t4_register_uld(struct uld_info *);
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int t4_unregister_uld(struct uld_info *);
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int t4_activate_uld(struct adapter *, int);
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int t4_deactivate_uld(struct adapter *, int);
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void t4_iscsi_init(struct adapter *, u_int, const u_int *);
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int uld_active(struct adapter *, int);
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#endif
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#endif
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