67 lines
2.7 KiB
C
67 lines
2.7 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_SPIREG_H
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#define ARM_AT91_AT91_SPIREG_H
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#define SPI_CR 0x00 /* CR: Control Register */
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#define SPI_CR_SPIEN 0x1
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#define SPI_CR_SPIDIS 0x2
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#define SPI_CR_SWRST 0x8
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#define SPI_MR 0x04 /* MR: Mode Register */
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#define SPI_MR_MSTR 0x01
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#define SPI_MR_PS 0x02
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#define SPI_MR_PCSDEC 0x04
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#define SPI_MR_DIV32 0x08
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#define SPI_MR_MODFDIS 0x10
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#define SPI_MR_LLB 0x80
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#define SPI_MR_PSC_CS0 0xe0000
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#define SPI_MR_PSC_CS1 0xd0000
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#define SPI_MR_PSC_CS2 0xb0000
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#define SPI_MR_PSC_CS3 0x70000
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#define SPI_RDR 0x08 /* RDR: Receive Data Register */
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#define SPI_TDR 0x0c /* TDR: Transmit Data Register */
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#define SPI_SR 0x10 /* SR: Status Register */
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#define SPI_SR_RDRF 0x00001
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#define SPI_SR_TDRE 0x00002
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#define SPI_SR_MODF 0x00004
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#define SPI_SR_OVRES 0x00008
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#define SPI_SR_ENDRX 0x00010
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#define SPI_SR_ENDTX 0x00020
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#define SPI_SR_RXBUFF 0x00040
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#define SPI_SR_TXBUFE 0x00080
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#define SPI_SR_SPIENS 0x10000
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#define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */
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#define SPI_IDR 0x18 /* IDR: Interrupt Disable Regsiter */
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#define SPI_IMR 0x1c /* IMR: Interrupt Mask Regsiter */
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#define SPI_CSR0 0x30 /* CS0: Chip Select 0 */
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#define SPI_CSR_CPOL 0x01
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#define SPI_CSR1 0x34 /* CS1: Chip Select 1 */
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#define SPI_CSR2 0x38 /* CS2: Chip Select 2 */
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#define SPI_CSR3 0x3c /* CS3: Chip Select 3 */
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#endif /* ARM_AT91_AT91_SPIREG_H */
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