116 lines
3.9 KiB
C
116 lines
3.9 KiB
C
/*
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* AMD Am83C30 serial communication controller registers.
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*
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* Copyright (C) 1996 Cronyx Engineering.
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* Author: Serge Vakulenko, <vak@cronyx.ru>
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*
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* This software is distributed with NO WARRANTIES, not even the implied
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* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Authors grant any other persons or organisations permission to use
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* or modify this software as long as this message is kept with the software,
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* all derivative works or modified versions.
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*
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* Cronyx Id: am8530.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $
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* $FreeBSD$
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*/
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/*
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* Read/write registers.
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*/
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#define AM_IVR 2 /* rw2 - interrupt vector register */
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#define AM_DAT 8 /* rw8 - data buffer register */
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#define AM_TCL 12 /* rw12 - time constant low */
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#define AM_TCH 13 /* rw13 - time constant high */
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#define AM_SICR 15 /* rw15 - status interrupt control reg */
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/*
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* Write only registers.
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*/
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#define AM_CR 0 /* w0 - command register */
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#define AM_IMR 1 /* w1 - interrupt mode register */
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#define AM_RCR 3 /* w3 - receive control register */
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#define AM_PMR 4 /* w4 - tx/rx parameters and modes reg */
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#define AM_TCR 5 /* w5 - transmit control register */
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#define AM_SAF 6 /* w6 - sync address field */
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#define AM_SFR 7 /* w7 - sync flag register */
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#define AM_MICR 9 /* w9 - master interrupt control reg */
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#define AM_MCR 10 /* w10 - misc control register */
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#define AM_CMR 11 /* w11 - clock mode register */
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#define AM_BCR 14 /* w14 - baud rate control register */
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/*
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* Read only registers.
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*/
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#define AM_SR 0 /* r0 - status register */
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#define AM_RSR 1 /* r1 - receive status register */
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#define AM_IPR 3 /* r3 - interrupt pending register */
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#define AM_MSR 10 /* r10 - misc status register */
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/*
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* Enhanced mode registers.
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* In enhanced mode registers PMR(w4), TCR(w5) become readable.
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*/
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#define AM_FBCL 6 /* r6 - frame byte count low */
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#define AM_FBCH 7 /* r7 - frame byte count high */
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#define AM_RCR_R 9 /* r9 - read RCR(w3) */
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#define AM_MCR_R 11 /* r11 - read MCR(w10) */
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#define AM_SFR_R 14 /* r14 - read SFR(w7') */
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#define AM_A 32 /* channel A offset */
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/*
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* Interrupt vector register
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*/
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#define IVR_A 0x08 /* channel A status */
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#define IVR_REASON 0x06 /* interrupt reason mask */
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#define IVR_TXRDY 0x00 /* transmit buffer empty */
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#define IVR_STATUS 0x02 /* external status interrupt */
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#define IVR_RX 0x04 /* receive character available */
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#define IVR_RXERR 0x06 /* special receive condition */
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/*
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* Interrupt mask register
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*/
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#define IMR_EXT 0x01 /* ext interrupt enable */
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#define IMR_TX 0x02 /* ext interrupt enable */
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#define IMR_PARITY 0x04 /* ext interrupt enable */
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#define IMR_RX_FIRST 0x08 /* ext interrupt enable */
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#define IMR_RX_ALL 0x10 /* ext interrupt enable */
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#define IMR_RX_ERR 0x18 /* ext interrupt enable */
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#define IMR_WD_RX 0x20 /* wait/request follows receiver fifo */
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#define IMR_WD_REQ 0x40 /* wait/request function as request */
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#define IMR_WD_ENABLE 0x80 /* wait/request pin enable */
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/*
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* Master interrupt control register
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*/
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#define MICR_VIS 0x01 /* vector includes status */
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#define MICR_NV 0x02 /* no interrupt vector */
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#define MICR_DLC 0x04 /* disable lower chain */
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#define MICR_MIE 0x08 /* master interrupt enable */
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#define MICR_HIGH 0x10 /* status high */
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#define MICR_NINTACK 0x20 /* interrupt masking without INTACK */
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#define MICR_RESET_A 0x80 /* channel reset A */
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#define MICR_RESET_B 0x40 /* channel reset B */
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#define MICR_RESET_HW 0xc0 /* force hardware reset */
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/*
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* Receive status register
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*/
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#define RSR_FRME 0x10 /* framing error */
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#define RSR_RXOVRN 0x20 /* rx overrun error */
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/*
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* Command register
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*/
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#define CR_RST_EXTINT 0x10 /* reset external/status irq */
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#define CR_TX_ABORT 0x18 /* send abort (SDLC) */
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#define CR_RX_NXTINT 0x20 /* enable irq on next rx character */
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#define CR_RST_TXINT 0x28 /* reset tx irq pending */
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#define CR_RST_ERROR 0x30 /* error reset */
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#define CR_RST_HIUS 0x38 /* reset highest irq under service */
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