a381b05232
- Add pl310.disable tunable to disable L2 cache altogether. In
order to make sure that it's 100% disabled we use cache event
counters for cache line eviction and read allocate events
and panic if any of these counters increased. This is purely
for debugging purpose
- Direct access DEBUG_CTRL and CTRL might be unavailable in
unsecure mode, so use platform-specific functions for
these registers
- Replace #if 1 with proper erratum numbers
- Add erratum 753970 workaround
- Remove wait function for atomic operations
- Protect cache operations with spin mutex in order to prevent race condition
- Disable instruction cache prefetch and make sure data cache
prefetch is enabled in OMAP4-specific intialization
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| .. | ||
| arm | ||
| at91 | ||
| broadcom/bcm2835 | ||
| compile | ||
| conf | ||
| econa | ||
| include | ||
| lpc | ||
| mv | ||
| s3c2xx0 | ||
| sa11x0 | ||
| tegra | ||
| ti | ||
| versatile | ||
| xscale | ||