a3bd38c3ab
Freescale added the E.D profile to e500mc and derivative cores. From Freescale's EREF reference manual this is enabled by a bit in HID0 and should otherwise default to traditional debug. However, none of the Freescale cores support that bit, and instead always use E.D. This results in kernel panics using the standard debug on e500mc+ cores. Enhanced debug allows debugging of interrupts, including critical interrupts, as it uses a different save/restore registers (srr*). At this time we don't use this ability, so instead share the core of the debug handler code between both handlers. MFC after: 3 weeks |
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